Search

Real-time hardware-in-the-loop-(HIL) simulation integration is now a fundamental component of the power electronics control design cycle. This integration is required to test the efficacy of controller implementations. Even though hardware-in-the-loop-(HIL) tools use FPGA devices with computing power that is rapidly evolving, developers constantly need to balance the ease of deploying models with acceptable accuracy. This study introduces a methodology for implementing a full-bridge inverter and buck converter utilising the associate-discrete-circuit-(ADC) model, which is optimised for real-time simulator applications. Additionally, this work introduces a new approach for choosing ADC parameter values by using the artificial-bee-colony-(ABC) algorithm, the firefly algorithm (FFA), and the genetic algorithm (GA). The implementation of the ADC-based model enables the development of a consistent architecture in simulation, regardless of the states of the switches. The simulation results demonstrate the efficacy of the proposed methodology in selecting optimal parameters for an ADC-switch-based full-bridge inverter and buck converter. These results indicate a reduction in overshoot and settling time observed in both the output voltage and current of the chosen topologies.