19 results on '"Sakhare, Sushil"'
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2. A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs
3. Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications
4. JSWof 5.5 MA/cm2 and RA of 5.2-Ω · μm2 STT-MRAM Technology for LLC Application.
5. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks
6. Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
7. Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems
8. Impact of Interconnect Multiple-Patterning Variability on SRAMs
9. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
10. A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs
11. Simplistic Simulation-Based Device-VT-Targeting Technique to Determine Technology High-Density LELE-Gate-Patterned FinFET SRAM in Sub-10 nm Era
12. Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM
13. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
14. Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node
15. Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM
16. Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node
17. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
18. Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM
19. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
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