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3. Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications

Author

Huynh-Bao, Trong, primary, Veloso, Anabela, additional, Sakhare, Sushil, additional, Matagne, Philippe, additional, Ryckaert, Julien, additional, Perumkunnil, Manu, additional, Crotti, Davide, additional, Yasin, Farrukh, additional, Spessot, Alessio, additional, Furnemont, Arnaud, additional, Kar, Gouri, additional, and Mocuta, Anda, additional

Published
2019
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4. JSWof 5.5 MA/cm2 and RA of 5.2-Ω · μm2 STT-MRAM Technology for LLC Application.

Author

Sakhare, Sushil, Rao, Siddharth, Perumkunnil, Manu, Couet, Sebastien, Crotti, Davide, Van Beek, Simon, Furnemont, Arnaud, Catthoor, Francky, and Kar, Gouri Sankar

Subjects
*STATIC random access memory, *MAGNETIC tunnelling, *RANDOM access memory, *BREAKDOWN voltage, *TECHNOLOGY
Abstract

Due to the complexity of device processing, the trade-off between yield and area has resulted in diminishing rate of scaling for the high-density static random access memory (SRAM) cell at advanced CMOS nodes. An introduction of extreme ultraviolet (EUV) and multipatterning has added additional cost to technology in order to realize 3-D device structure and ultrascaled metal routing. In this era, spin-transfer torque (STT)-MRAM technology can provide an alternative to high-density SRAM and for the last level cache (LLC) applications. In this article, we discuss the memory design and technology tradeoff to enable the STT-MRAM as a viable option. We have realized the technology over 300-mm wafer, measuring 1 million samples to build a SPICE model for circuit simulation. Occupying up to 83.3% of an area that of SRAM macro has been designed and simulated for the scaled 5-nm CMOS node. The simulated MRAM macro shows the best read and write access time of 3.1 and 6.2 ns, respectively. Magnetic tunneling junction (MTJ) pillar of 38-nm diameter is realized at 90-nm pitch, measuring resistance area (RA) of 5.2-Ω ⋅ μm2, Jsw of 5.5 MA/cm2 with improved Δ avg of 70, and breakdown voltage of 0.99 V. The energy comparison shows increasing gains versus SRAM for the increasing cache sizes crossing over at of 0.3 and 4 MB for the single-cycle read and write operations, respectively. [ABSTRACT FROM AUTHOR]

Published
2020
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5. Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Author

Komalan, Manu, primary, Rock, Oh Hyung, additional, Hartmann, Matthias, additional, Sakhare, Sushil, additional, Tenllado, Christian, additional, Gomez, Jose Ignacio, additional, Kar, Gouri Sankar, additional, Furnemont, Arnaud, additional, Catthoor, Francky, additional, Senni, Sophiane, additional, Novo, David, additional, Gamatie, Abdoulaye, additional, and Torres, Lionel, additional

Published
2018
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6. Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.

Author

Trong Huynh-Bao, Veloso, Anabela, Sakhare, Sushil, Matagne, Philippe, Ryckaert, Julien, Perumkunnil, Manu, Crotti, Davide, Yasin, Farrukh, Spessot, Alessio, Furnemont, Arnaud, Kar, Gouri, and Mocuta, Anda

Subjects
TRANSISTORS, COINTEGRATION, ELECTROSTATICS, OXIDATION kinetics, MAGNETIC fields
Abstract

We present for the first time a co-integrated FinFET with vertical nanosheet transistor (VFET) process on a 300 mm silicon wafer for STT-MRAM applications and its related avenues with a holistic design-technology-co-optimization (DTCO) and power-performance-area-cost (PPAC) approach. The STT-MRAM bitcell and a 2 Mbit macro have been optimized and designed to address the viability of the co-integration process and advantages of vertical channel transistors for STT-MRAM selectors. An architectural system simulator GEM5 has been also employed with Polybench workloads to assess energy saving at system-level. In order to enable this co-integration, four extra masks are required, which costs below 10% in embedded chips. A 36% area reduction can be achieved for the STT-MRAM bitcell implemented with VFET selectors. With a UVLT flavor, the STT-MRAM bitcell comprising of 3-nanosheet could deliver the same performance of the 4-fin LVT FinFET selector. A 2 Mbit STT-MRAM macro designed with VFET selector can offer a 17% and a 21% reduction for read access latency and energy per operation respectively, and a 10% for write energy per operation. A 7% energy saving for the STT-MRAM L2 cache using VFET selector has been observed at the system level with Polybench workloads. [ABSTRACT FROM AUTHOR]

Published
2019
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8. Impact of Interconnect Multiple-Patterning Variability on SRAMs

Author

Karageorgos, Ioannis, Stucchi, Michele, Raghavan, Praveen, Ryckaert, Julien, Tokei, Zsolt, Verkest, Diederik, Baert, Rogier, Sakhare, Sushil, Dehaene, Wim, Nebel, Wolfgang, and Atienza, David

Subjects
interconnects, variability, Back End of Line, multiple patterning, SRAM, variation aware design, LELE, multi patterning, BEOL, EUV, Self Aligned, SADP, variation, process variation
Abstract

The introduction of Multiple Patterning (MP) in sub-32nm technology nodes may pose severe variability problems in wire resistance and capacitance of IC circuits. In this paper we evaluate the impact of this variability on the performance of SRAM cell arrays based on the 10nm technology node, for a relevant range of process variation assumptions. The MP options we consider are the triple Litho-Etch (LE^3) and the Self Aligned Double Patterning (SADP), together with Single Patterning Extreme-UV (EUV). In addition to the analysis of the worst-case variability scenario and the impact on SRAM performance, we propose an analytical formula for the estimation of SRAM read time penalty, using the RC variation of the bit line and the array size as input parameters. This formula, verified with SPICE simulations, allows a fast extraction of the statistical distribution of the read time penalty, using the Monte-Carlo method. Results on each patterning option are presented and compared. ispartof: pages:609-612 ispartof: Proc. DATE vol:2015 pages:609-612 ispartof: Design, Automation and Test in Europe Conference and Exhibition (DATE) location:Grenoble, France date:9 Mar - 13 Mar 2015 status: published

Published
2015

13. DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Author

Ryckaert, Julien, additional, Raghavan, Praveen, additional, Schuddinck, Pieter, additional, Trong, Huynh Bao, additional, Mallik, Arindam, additional, Sakhare, Sushil S., additional, Chava, Bharani, additional, Sherazi, Yasser, additional, Leray, Philippe, additional, Mercha, Abdelkarim, additional, Bömmels, Jürgen, additional, McIntyre, Gregory R., additional, Ronse, Kurt G., additional, Thean, Aaron, additional, Tökei, Zsolt, additional, Steegen, An, additional, and Verkest, Diederik, additional

Published
2015
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17. DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Author

Sturtevant, John L., Capodieci, Luigi, Ryckaert, Julien, Raghavan, Praveen, Schuddinck, Pieter, Trong, Huynh Bao, Mallik, Arindam, Sakhare, Sushil S., Chava, Bharani, Sherazi, Yasser, Leray, Philippe, Mercha, Abdelkarim, Bömmels, Jürgen, McIntyre, Gregory R., Ronse, Kurt G., Thean, Aaron, Tökei, Zsolt, Steegen, An, and Verkest, Diederik

Published
2015
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