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The Medipix4 chip is the latest member in the Medipix/Timepix family of hybrid pixel detector chips aimed at high-rate spectroscopic X-ray imaging using high-Z materials. It can be tiled on all 4 sides making it ideal for constructing large-area detectors with minimal dead area. The chip is designed to read out a sensor of 320 x 320 pixels with dimensions of 75 {\mu}m x 75 {\mu}m or 160 x 160 pixels with dimensions of 150 {\mu}m x 150 {\mu}m. The readout architecture features energy binning of the single photons, which includes charge sharing correction for hits with energy spread over adjacent pixels. This paper presents the specifications, architecture, and circuit implementation of the chip, along with the first electrical measurements.

This paper analyzes the design space stability of negative capacitance double gate junctionless FETs (NCDG JLFET). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77K to 400K. This approach has been assessed with numerical TCAD simulations.

In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, for the first time, our model predicts that the negative capacitance minimizes short channel effects and enhances current overdrive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels (0.1 {\textmu}A/{\textmu}m). Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.

Quantum computing (QC) has already entered the industrial landscape and several multinational corporations have initiated their own research efforts. So far, many of these efforts have been focusing on superconducting qubits, whose industrial progress is currently way ahead of all other qubit implementations. This paper briefly reviews the progress made on the silicon-based QC platform, which is highly promising to meet the scale-up challenges by leveraging the semiconductor industry. We look at different types of qubits, the advantages of silicon, and techniques for qubit manipulation in the solid state. Finally, we discuss the possibility of co-integrating silicon qubits with FET-based, cooled front-end electronics, and review the device physics of MOSFETs at deep cryogenic temperatures.

In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals, high-energy ionizing radiation or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperature from 77K to 400K. The validity of the approach is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation from deep depletion to accumulation and linear to saturation.

This paper presents a generalization of the charge-based model for ultrathin junctionless double-gate (JLDG) field-effect transistors (FETs) by including quantum electron density. The analytical derivation relies on a first-order correction to the infinite quantum well. When restricting the analysis to the first and second quantized states, the free carrier charge distribution and the current in an ultrathin body JLDG FETs are in agreement with numerical TCAD simulations in all the regions of operation, i.e., from deep depletion to accumulation and from linear to saturation.

This work revisits the classical concept of electric energy and suggests that the common definition is likely to generate large errors when dealing with nanostructures. For instance, deriving the electrostatic energy in semiconductors using the traditional formula fails at giving the correct electrostatic force between capacitor plates and reveals the existence of an extra contribution to the standard electrostatic energy. This additional energy is found to proceed from the generation of space charge regions which are predicted when combining electrostatics laws with semiconductor statistics, such as for accumulation and inversion layers. On the contrary, no such energy exists when relying on electrostatics only, as for instance when adopting the so-called full depletion approximation. The same holds for charged or neutral insulators that are still consistent with the customary definition, but which are in fact singular cases. In semiconductors, this additional free energy can largely exceed the energy gained by the dipoles, thus becoming the dominant term. Consequently, erroneous electrostatic forces in nanostructure systems such as for MEMS and NEMS as well as incorrect energy calculations are expected using the standard definition. This unexpected result clearly asks for a generalization of electrostatic energy in matter in order to reconcile basic concepts and to prevent flawed force evaluation in nanostructures with electrical charges., Comment: 24 pages 8 figures