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The impact of bulk and surface defect states on the vibrational and optical properties of step-graded epitaxial GaAs₁₋ySby (0 ≤ y ≤ 1) materials with and without chemical surface treatment by (NH₄)₂S was investigated. Tunable antimony (Sb) composition GaAs₁₋ySby epitaxial layers, grown by solid source molecular beam epitaxy (MBE), were realized on GaAs and Si substrates by varying key growth parameters (e.g., Sb/Ga flux ratio, growth temperature). Raman and photoluminescence (PL) spectroscopic analysis of (NH₄)₂S-treated GaAs₁₋ySby epitaxial layers revealed composition-independent Raman spectral widths and enhanced PL intensity (1.3x) following (NH₄)₂S surface treatment, indicating bulk defect-minimal epitaxy and a reduction in the surface recombination velocity corresponding to reduced surface defect sites, respectively. Moreover, quantification of the luminescence recombination mechanisms across a range of measurement temperatures and excitation intensities (i.e., varying laser power) indicate the presence of free-electron to neutral acceptor pair or Sb-defect-related recombination pathways, with detectable bulk defect recombination discernible only in binary GaSb PL spectra. In addition, PL analysis of the short- and long-term thermodynamic stability of sulfur-treated GaAs₁₋ySby/Al₂O₃ heterointerfaces revealed an absence of quantifiable atomic interdiffusion or native oxide formation. Leveraging the combined Raman and PL analysis herein, the quality of the heteroepitaxial step-graded epitaxial GaAs₁₋ySby materials can be optimized for optical devices.

In this paper, for the first time, the performance analysis of short channel In₀.₅₃Ga₀.₄₇As quantum well (QW) 3-D tri-gate technology with advanced high-κ gate dielectric, TaSiOx is presented. We benchmark the projected performance of sub-10 nm In₀.₅₃Ga₀.₄₇As transistor technology as a function of fin width, fin aspect ratio, and gate length scaling based on present-day lithographic advancement aiding InGaAs QW tri-gate technology as a replacement to Si for sub-10 nm transistor technology. The highly scaled oxide (EOT ∼ 12Å) while retaining superior interfacial properties (Dit ∼ 4 × 10¹¹ cm⁻²eV⁻¹) provides higher ON current for given idle performance. Furthermore, the simulated In₀.₅₃Ga₀.₄₇As tri-gate transistor exhibits superior gate electrostatic control with low OFF-state current (IOFF) ∼ 24.5 nA/μm, peak transconductance (gm) ∼ 2 mS/ μm and high ION/IOFF ratio ∼ 2.3 × 10³, aiding the case of alternate channel transistors for high-speed and low-power CMOS logic.

The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications. Master of Science