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This paper discusses the fabrication of SiGe channel for Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator (UTBB FDSOI) MOSFETs, FinFETs and Nano Wire FETs (NWFETs). Enrichment conditions need to be tuned to avoid excessive Ge pile-up on tensile-strained planar Si films due to lower Ge diffusion. Patterning SiGe Fins in thick blanket SiGe layers faces the crystal quality limits set by plastic relaxation beyond critical thickness. As an alternative, Ge enrichment of pre-existing Si Fins requires conformal SiGe growth and can produce strained SiGe Fins up to 50% without significant relaxation, independently from Fin height. Enrichment requirements for NWFETs are identical to those of planar devices. As a result, NWFETs benefit from both SiGe mechanical stability and uniaxial compressive strain performance enhancement.

Non-Volatile Resistive Memory (NVRM) such as Phase-Change Memory, Oxide-based Memory and Conductive Bridging Memory has rapidly increased in maturity in the last decade. In a memory market context dominated by DRAM and Flash technologies, the evolving memory hierarchy and the strong differentiation of the applications portfolio represent a real opportunity for NVRM to emerge. The real revolution of this technology resides in its versatility made possible by general trade-offs existing between the different NVRM performances, highlighted in the last years by the research and the development in several fields (e.g. materials science, engineering, etc.). We present here some of these trade-offs, and how they can be used to target specific applications.

Oxide based resistive memories (OxRAMs) is one of the potential candidates for non-volatile logic circuits and neuromorphic circuits in the applications of wearable devices, internet of things (IoT), cloud computing, and big-data processing. One of the main OxRAMs issue is the noise behavior of the high resistance state (HRS). In this work, we will demonstrate a hybrid (CMOS logic plus ReRAM devices) Non Volatile Flip Flop designed to face OxRAM variability. Concerning neuromorphic circuits, we will focus on the impact of resistance variability on the performance of Convolutional Neural Network (CNN) systems for visual pattern recognition applications.

Here, we demonstrate a new process to fabricate tensily strained Si On Insulator substrates (sSOI). The process is based on the epitaxial growth of Si1-xGex on SOI substrate, the partial amorphization and crystallization of the Si / Si1-xGex bilayers and the selective removal of the top Si1-xGex film. Si tensile stress higher than 1.4 GPa is obtained. Complementary Metal Oxide Semiconductor Fully Depleted- SOI (CMOS FD-SOI) devices at 14 nm node design rules were fabricated on top of such substrate. For nFET devices, improvement in mobility is demonstrated with respect to devices built on standard SOI substrates.

Germanium enrichment process also known as condensation can be used for the integration of stressors in the fully depleted silicon on insulator technology. Using multi-physics modeling combined with advanced TEM characterization we studied the formation of stressors with condensation. We first observed in blanket 1D structures that the diffusion rate is substantially reduced during Ge condensation compared to the typical diffusion in neutral atmosphere. We postulate this is due to the injection of interstitial at the oxide/SiGe interface and to a reduced stress effect on the kinetics. We then studied self-aligned in plane stressors (SAIPS) formed in the source/drain region using localized Ge condensation. It is shown that the SAIPS methodology almost doubles the channel stress generated by the source drain stressor. Combining Si0.65Ge0.35 and SAIPS source/drain stressors with in-situ Si0.79Ge0.21 strained channel allows achieving a stress of -2 GPa in the p-type channel with gate first architecture.

In this work we combine experimental data and first principles calculations to investigate the conductive filament (CF) creation in HfO2 based resistive switching memories. First, we propose that the CF in HfO2-based resistive OxRAMs is due to HfOx sub-oxides, possibly assuming a tetragonal symmetry with x[?]1.5. Second, we demonstrate that Frenkel-Pair formation is favored by electron injection and by the adoption of oxygen reactive electrodes with low work function, such as Ti. Finally, endurance tests on a memory cell with Ti as the top electrode were performed to assess its cycling stability. Endurance up to 108 cycles with optimized set conditions has been demonstrated.

In this paper, we will make a general overview of different technological approaches suitable for charge storage memories. Several solutions to extend the floating gate Flash memory technology to the 22nm nodes and beyond, are presented. In particular, new modules (discrete traps memories, and more specifically silicon nanocrystal memories), new materials (as high-k materials for the interpoly layer) and innovative architectures (as FinFlash memories) are discussed. Moreover, hybrid approaches which make use of organic molecules as storage sites will be also introduced. Finally, the main theoretical limits of ultra-scaled charge storage memories (i.e. reliability issues linked to few electron phenomena) will be analyzed, opening the path to the introduction of disruptive technologies based on new storage mechanisms (as Phase-Change Memories and Oxide resistive RAMs).

This paper proposes a novel pre-coding method that enables bypassing the soldering reflow issue in resistive memory devices called RRAM. This method is based on the difference between forming and set voltages distributions to discriminate virgin memory cells from those in which data were pre-coded before the soldering step. This procedure enables data recovery through the application of a voltage pulse over the whole memory array. This method, demonstrated on bipolar HfO2-based resistive elements, can be extended to all RRAM devices that exhibit a significant margin between forming and set voltages distributions.