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This paper presents a methodology to design reconfigurable switched-capacitor delta-sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low-bandwidth, medium-to-high-resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power-optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade-off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18-µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach.

This paper presents a low-power switched-capacitor $Delta Sigma$ modulator for digital hearing-aid applications that features a novel summing successive approximation (SAR). The summing SAR performs multi-bit quantization together with the analog addition required in feed-forward (FF) $Delta Sigma$ modulator $(Delta Sigma {rm M})$ topologies, with no attenuation of the input signals and no need for amplifiers. The prototype is implemented in a 0.18-$mu$ m CMOS technology and its measurements demonstrate a dynamic range of 88 dB in 10 kHz bandwidth while consuming 155 $mu$W from a 1.8 V supply. The combined use of passive addition and SAR quantization reduces the complexity and power consumption of the modulator. The summing SAR ADC quantizer results in a calculated power saving of 40% when compared to a multi-bit FF $Delta Sigma$M using active addition and flash quantization.

The paper presents a reconfigurable Delta-Sigma Modulator (¿SM) suitable for three operation modes, whose application ranges from bio-potential signal monitoring to hearing aids. A feed-forward 2nd-order SC ¿SM architecture with 4-bit quantizer is selected according to an analytic power optimization procedure. The ¿SM features programmable sampling capacitors in the first integrator and novel reconfigurable power-gated OTAs to adjust power consumption in each operation mode. An asynchronous embedded SAR converter implements low-power quantization and passive addition in the feed-forward topology. The prototype is implemented in a 0.18µm CMOS technology and operates from a supply voltage of 1V. Measurements show peak SNDRs from 99 to 75dB for signal bandwidths spanning from 256Hz to 16kHz, achieving figures of merit which are almost constant in the different modes, and range from 0.20 to 0.27pJ/c.s.

This paper introduces a 3D-integrated image sensor with high dynamic range, high frame rate and high resolution capabilities. A robust algorithm for dynamic range extension with low sensitivity to circuit non-idealities and based on multiple exposures is presented. The impact of the TSV diameter over the dynamic range and frame rate performance is studied allowing the choice of the best 3D technology for the required performance. ispartof: pages:836-839 ispartof: Proceedings of DATE pages:836-839 ispartof: DATE location:Dresden date:12 Mar - 16 Mar 2012 status: published

In this paper we present a low-power switched-capacitor In this paper we present a low-power switched-capacitor ¿S modulator for digital hearing-aid applications. The circuit adopts a novel summing successive approximation (SAR) block to perform multi-bit quantization together with the analog addition that is required in feed-forward topologies. The use of passive addition and SAR operation helps in reducing the complexity and power consumption of the modulator. The prototype is implemented in a 180 nm CMOS technology and measurements demonstrate 88 dB of dynamic range in a 10 kHz band while consuming 155µW from a 1.8V supply.

Unlike conventional CMOS imaging, a singlephoton imager detects each individual photon impinging ona detector, accumulating the number of photons during acertain time window and not the charge generated by the allthe photons hitting the detector during said time window.The latest developments in the semiconductor industryare allowing faster and more complex chips to be designedand manufactured. With these developments in mind we areworking towards the next step in single photon X-ray imaging:energy sensitive pixel readout chips. The goal is not only to detect and count individual photons, but also to measure the charge deposited in the detector by each photon, and consequently determine its energy. Basically, we are aiming at a spectrometer-in-a-pixel, or a 'color X-ray camera'. The approach we have followed towards this goal is the design of small analog-to-digital-converters at the pixel level, together with a very fast digital readout from the pixels to the periphery of the chip, where the data will be transmitted off-chip. We will present here the design and measurement on prototype chips of two different 4-bit pixel level ADCs. The ADCs are optimized for very small area and low power, with a resolution of 4-bits and a sample rate of 1 Msample/s. The readout architecture is based around current-mode sense amplifiers and asynchronous token-passing between the pixels. This is done in order to achieve event-by-event readout and, consequently, on-line imaging. We need to read eventby-event (photon-by-photon), because we cannot have memory on the pixels due to obvious size constraints. We use current-mode sense amplifiers because they perform very well in similar applications as very fast static-RAM readout.

Single-photon counting hybrid pixel detectors have shown to be a valid alternative to other types of X-ray imaging devices due to their high sensitivity, low noise, linear behavior and wide dynamic range. One important advantage of these devices is the fact that detector and readout electronics are manufactured separately. This allows the use of industrial state-of-the-art CMOS processes to make the readout electronics, combined with a free choice of detector material (high resistivity Silicon, GaAs or other). By measuring not only the number of X-ray photons but also their energies (or wavelengths), the information content of the image increases, given the same X-ray dose. We have studied several possibilities of adding energy sensitivity to the single photon counting capability of hybrid pixel detectors, by means of pixel-level analog-to-digital converters. We show the results of simulating different kinds of analog-to-digital converters in terms of power, area and speed.

A new front-end has been implemented on a pixel detector readout chip developed in a commercial 0.25?m CMOS technology for the ALICE and LHCb experiments. This technology proves to be radiation tolerant when special layout techniques are used, and provides sufficient density for these applications. A non-standard topology was used for the front-end, to achieve low noise and fast return to zero of the preamplifier to be immune to pile-up of subsequent input signals. The chip is a matrix of 32 columns each containing 256 readout cells. Each readout cell comprises this frontend and digital readout circuitry, and has a static power consumption of about 60 ?W. The complete readout cell will be described, but the paper will be mainly focussed on the front-end section.