Aguilar-Melchor, Carlos, Deneuville, Jean-Christophe, Dion, Arnaud, Howe, James, Malmain, Romain, Migliore, Vincent, Nawan, Mamuri, Nawaz, Kashif, Centre National de la Recherche Scientifique - CNRS (FRANCE), Ecole Nationale de l'Aviation Civile - ENAC (FRANCE), Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Institut National des Sciences Appliquées de Toulouse - INSA (FRANCE), Institut Supérieur de l'Aéronautique et de l'Espace - ISAE-SUPAERO (FRANCE), Institut Eurécom (FRANCE), SandboxAQ (USA), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Technology Innovation Institute - TII (United Arab Emirates), Département d'Ingénierie des Systèmes Complexes - DISC (Toulouse, France), Laboratoire d'Analyse et d'Architecture des Systèmes - LAAS (Toulouse, France), SandboxAQ, Ecole Nationale de l'Aviation Civile (ENAC), Département d'Ingénierie des Systèmes Complexes (DISC), Institut Supérieur de l'Aéronautique et de l'Espace (ISAE-SUPAERO), Eurecom [Sophia Antipolis], Équipe Tolérance aux fautes et Sûreté de Fonctionnement informatique (LAAS-TSF), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and Technology Innovation Institute (TII)
International audience; While hardware implementations allow the production of highly efficient and performance oriented designs, exploiting features such as parallelization, their longer time to code and implement often bottlenecks rapid prototyping. On the other hand, high-level synthesis (HLS) tools allow for faster experimentation of software code to a hard- ware platform while demonstrating a reasonable extrapolation of the expected hardware behavior. In this work, we attempt to show a rapid, fast prototyping of the well known HQC algorithm, using HLS, and show how with a modification of certain parameters, varying degrees of comparable results can be obtained. These results, in turn, could be used as a guide for HDL-RTL developers to enhance their designs and better prototyping time in the future. Additionally, we also demonstrate that it is possible to benefit from HQC’s versatility; by achieving a low hardware footprint whilst also maintaining good performances, even on low-cost FPGA devices, which we demonstrate on the well known Artix-7 xc7a100t-ftg256-1.