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297 results on '"Sassatelli, Gilles"'

1. Towards Sustainable Low Carbon Emission Mini Data Centres

Author

Samaye, Ismael, Leloup, Paul, Sassatelli, Gilles, and Gamatié, Abdoulaye

Subjects
Computer Science - Hardware Architecture
Abstract

Mini data centres have become increasingly prevalent in diverse organizations in recent years. They can be easily deployed at large scale, with high resilience. They are also cost-effective and provide highsecurity protection. On the other hand, IT technologies have resulted in the development of ever more energy-efficient servers, leading to the periodic replacement of older-generation servers in mini data centres. However, the disposal of older servers has resulted in electronic waste that further aggravates the already critical e-waste problem. Furthermore, despite the shift towards more energy-efficient servers, many mini data centres still rely heavily on high-carbon energy sources. This contributes to data centres' overall carbon footprint. All these issues are concerns for sustainability. In order to address this sustainability issue, this paper proposes an approach to extend the lifespan of older-generation servers in mini data centres. This is made possible thanks to a novel solar-powered computing technology, named Genesis, that compensates for the energy overhead generated by older servers. As a result, electronic waste can be reduced while improving system sustainability by reusing functional server hardware. Moreover, Genesis does not require server cooling, which reduces energy and water requirements. Analytical reasoning is applied to compare the efficiency of typical conventional mini data centre designs against alternative Genesis-based designs, in terms of energy, carbon emissions and exploitation costs.

Published
2024

2. Exploration of Performance and Energy Trade-offs for Heterogeneous Multicore Architectures

Author

Butko, Anastasiia, Bruguier, Florent, Novo, David, Gamatié, Abdoulaye, and Sassatelli, Gilles

Subjects
Computer Science - Distributed, Parallel, and Cluster Computing
Abstract

Energy-efficiency has become a major challenge in modern computer systems. To address this challenge, candidate systems increasingly integrate heterogeneous cores in order to satisfy diverse computation requirements by selecting cores with suitable features. In particular, single-ISA heterogeneous multicore processors such as ARM big.LITTLE have become very attractive since they offer good opportunities in terms of performance and power consumption trade-off. While existing works already showed that this feature can improve system energy-efficiency, further gains are possible by generalizing the principle to higher levels of heterogeneity. The present paper aims to explore these gains by considering single-ISA heterogeneous multicore architectures including three different types of cores. For this purpose, we use the Samsung Exynos Octa 5422 chip as baseline architecture. Then, we model and evaluate Cortex A7, A9, and A15 cores using the gem5 simulation framework coupled to McPAT for power estimation. We demonstrate that varying the level of heterogeneity as well as the different core ratio can lead to up to 2.3x gains in energy efficiency and up to 1.5x in performance. This study further provides insights on the impact of workload nature on performance/energy trade-off and draws recommendations concerning suitable architecture configurations. This contributes in fine to guide future research towards dynamically reconfigurable HSAs in which some cores/clusters can be disabled momentarily so as to optimize certain metrics such as energy efficiency. This is of particular interest when dealing with quality-tunable algorithms in which accuracy can be then traded for compute effort, thereby enabling to use only those cores that provide the best energy-efficiency for the chosen algorithm., Comment: 11 pages, 6 figure, 2 tables

Published
2019

3. A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures

Author

Ursu, Roman, Latif, Khalid, Novo, David, Selva, Manuel, Gamatie, Abdoulaye, Sassatelli, Gilles, Khabi, Dmitry, and Cheptsov, Alexey

Subjects
Computer Science - Distributed, Parallel, and Cluster Computing
Abstract

Resource allocation is today an integral part of cloud infrastructures management to efficiently exploit resources. Cloud infrastructures centers generally use custom built heuristics to define the resource allocations. It is an immediate requirement for the management tools of these centers to have a fast yet reasonably accurate simulation and evaluation platform to define the resource allocation for cloud applications. This work proposes a framework allowing users to easily specify mappings for cloud applications described in the AMALTHEA format used in the context of the DreamCloud European project and to assess the quality for these mappings. The two quality metrics provided by the framework are execution time and energy consumption., Comment: 2nd International Workshop on Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing DREAMCloud 2016 (arXiv:cs/1601.04675)

Published
2016

5. Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy

Author

Péneau, Pierre-Yves, Novo, David, Bruguier, Florent, Torres, Lionel, Sassatelli, Gilles, Gamatié, Abdoulaye, Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Weikum, Gerhard, Series Editor, Berekovic, Mladen, editor, Buchty, Rainer, editor, Hamann, Heiko, editor, Koch, Dirk, editor, and Pionteck, Thilo, editor

Published
2018
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15. High Performance SoC Design Using Magnetic Logic and Memory

Author

Zhao, Weisheng, Torres, Lionel, Cargnini, Luís Vitório, Brum, Raphael Martins, Zhang, Yue, Guillemenet, Yoann, Sassatelli, Gilles, Lakys, Yahya, Klein, Jacques-Olivier, Etiemble, Daniel, Ravelosona, Dafiné, Chappert, Claude, Mir, Salvador, editor, Tsui, Chi-Ying, editor, Reis, Ricardo, editor, and Choy, Oliver C. S., editor

Published
2012
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17. Towards Autonomous Scalable Integrated Systems

Author

Benoit, Pascal, Sassatelli, Gilles, Maurine, Philippe, Torres, Lionel, Azemard, Nadine, Robert, Michel, Clermidy, Fabien, Belleville, Marc, Puschini, Diego, Rebaud, Bettina, Brousse, Olivier, Almeida, Gabriel Marchesan, Nicolescu, Gabriela, editor, O'Connor, Ian, editor, and Piguet, Christian, editor

Published
2012
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20. Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions

Author

Elbaz, Reouven, Torres, Lionel, Sassatelli, Gilles, Guillemin, Pierre, Bardouillet, Michel, Martinez, Albert, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Gavrilova, Marina L., editor, Tan, C. J. Kenneth, editor, and Moreno, Edward David, editor

Published
2010
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21. The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems

Author

Brousse, Olivier, Sassatelli, Gilles, Gil, Thierry, Robert, Michel, Grize, François, Sanchez, Eduardo, Upegui, Andrés, Thoma, Yann, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Hornby, Gregory S., editor, Sekanina, Lukáš, editor, and Haddow, Pauline C., editor

Published
2008
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23. TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks

Author

Elbaz, Reouven, Champagne, David, Lee, Ruby B., Torres, Lionel, Sassatelli, Gilles, Guillemin, Pierre, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Paillier, Pascal, editor, and Verbauwhede, Ingrid, editor

Published
2007
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24. A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus

Author

Elbaz, Reouven, Torres, Lionel, Sassatelli, Gilles, Guillemin, Pierre, Bardouillet, Michel, Martinez, Albert, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Vounckx, Johan, editor, Azemard, Nadine, editor, and Maurine, Philippe, editor

Published
2006
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25. Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform

Author

Ngouanga, Alex, Sassatelli, Gilles, Torres, Lionel, Gil, Thierry, Suarez, André Borin, Susin, Altamiro Amadeu, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Dough, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Bertels, Koen, editor, Cardoso, João M. P., editor, and Vassiliadis, Stamatis, editor

Published
2006
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27. Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability

Author

Benoit, Pascal, Sassatelli, Gilles, Torres, Lionel, Demigny, Didier, Robert, Michel, Cambon, Gaston, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Pimentel, Andy D., editor, and Vassiliadis, Stamatis, editor

Published
2004
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30. L’impact énergétique des flux de données numériques

Author

Leduc, Thomas, Gamatié, Abdoulaye, Siret, Daniel, Sassatelli, Gilles, Robert, Michel, Centre de recherche nantais Architectures Urbanités (CRENAU ), Ambiances, Architectures, Urbanités (AAU), École Centrale de Nantes (ECN)-École nationale supérieure d'architecture de Nantes (ENSA Nantes)-Ministère de la Culture et de la Communication (MCC)-Centre National de la Recherche Scientifique (CNRS)-École nationale supérieure d'architecture de Grenoble (ENSAG ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA)-École Centrale de Nantes (ECN)-École nationale supérieure d'architecture de Nantes (ENSA Nantes)-Ministère de la Culture et de la Communication (MCC)-Centre National de la Recherche Scientifique (CNRS)-École nationale supérieure d'architecture de Grenoble (ENSAG ), Université Grenoble Alpes (UGA)-Université Grenoble Alpes (UGA), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), CNRS - Soutien MITI 2020 (Mission pour les Initiatives Transverses et Interdisciplinaires), Cellule énergie du CNRS, and Projet AVIDON

Subjects
[SHS.ARCHI]Humanities and Social Sciences/Architecture, space management, Photovoltaic potential of roofs, Spatial analysis (Statistics), Energy demand for household IT equipment, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, [SDE.ES]Environmental Sciences/Environmental and Society, ComputingMilieux_MISCELLANEOUS
Abstract

National audience

Published
2021

31. Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC

Author

Péneau, Pierre-Yves, Novo, David, Bruguier, Florent, Torres, Lionel, Sassatelli, Gilles, Gamatié, Abdoulaye, ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and ANR-15-CE25-0007,CONTINUUM,Continuum de Conception pour Noeuds de Calculs Energétiquement-Efficaces de Prochaine Génération(2015)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Hardware_MEMORYSTRUCTURES, Energy, Replacement Policy, Last-Level Cache, Performance, STT-MRAM, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]
Abstract

Modern architectures adopt large on-chip cache memory hierarchies with more than two levels. While this improves performance, it has a certain cost in area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance and energy. Well-known benefits of STT-MRAM are their near-zero static power and high density compared to volatile memories. Nonetheless, their high write latency may be detrimental to system performance. In order to mitigate this issue, we combine STT-MRAM with a recent cache replacement policy. The benefit of this combination is evaluated through experiments on SPEC CPU2006 benchmark suite, showing performance improvements of up to 10% and 14% compared to SRAM cache with LRU respectively on single and multicore systems. Moreover, the energy consumption is on average decreased by 20% for all platforms.

Published
2021

32. Towards a Flexible and Comprehensive Evaluation Approach for Adressing NVM Integration in Cache Hierarchy

Author

Péneau, Pierre-Yves, Bruguier, Florent, Novo, David, Sassatelli, Gilles, Gamatié, Abdoulaye, ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and ANR-15-CE25-0007,CONTINUUM,Continuum de Conception pour Noeuds de Calculs Energétiquement-Efficaces de Prochaine Génération(2015)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Hardware_MEMORYSTRUCTURES, Memory Hierarchy, Architecture, STT-MRAM, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], Design Space Exploration, Low-Power Design
Abstract

Emerging Non Volatile Memories (NVMs) are considered as potential candidates for replacing SRAM in future processor architectures. They offer higher density and near-zero leakage power, which is particularly interesting to reduce the overall system energy consumption. Nevertheless, NVMs can suffer from higher access costs in latency and dynamic energy consumption. Existing literature covers a large panel of techniques to mitigate these issues. However, design space explorations on NVMs are rarely discussed. In this paper, we present a comprehensive design exploration phase based on the NVSim tool to identify relevant NVM technology configuration. Selected designs are evaluated at Last-Level Cache (LLC) of multicore architectures by using a fast tracebased simulation. Energy-Delay-Product (EDP) is often used as a prime metric to evaluate NVMs integration. This papers discusses the usage of the EDP by adopting two perspectives of analysis : i) LLC only and ii) entire memory hierarchy. We show that the former, widespread in the literature, could lead to biased conclusions regarding of the impact of the NVM. It is therefore advisable to use a global perspective to accurately assess changes on the memory hierarchy.

Published
2021

36. Évaluation de deux architectures matérielles dédiées à l'inférence basée sur des réseaux de neurones convolutifs

Author

Devic, Guillaume, Gamatié, Abdoulaye, Sassatelli, Gilles, ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Gamatié, Abdoulaye, and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Architecture mémoire, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, GAPuino / GAP8, Intelligence artificielle, Système embarqué, Réseaux de neurones convolutifs, Coral Dev Board / EdgeTPU, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, Inférence
Abstract

International audience; Les systèmes embarqués sont de plus en plus utilisés pour exécuter des algorithmes d'intelligence artificielle, qui requièrent beaucoup de ressources matérielles, notamment en mémoire. Ces systèmes étant généralement dotés de ressources limitées, des architectures dédiées commencent à émerger, à l'image de celles proposées dans les deux cartes étudiées dans cet article : GAPuino et Coral Dev Board. Ces dernières s'appuient sur un accélérateur d'algorithmes d'inférence sous forme de réseau de neurones convolutifs (acronyme anglais, CNN). Nous évaluons ces deux cartes en implémentant un CNN entrainé avec la célèbre base de données MNIST. Nous étudions l'impact des architectures mémoires implantées dans les accélérateurs d'inférence, sur la performance et la puissance consommée par l'exécution des CNN.

Published
2020

37. Energy-Efficient Machine Learning on FPGA for Edge Devices: a Case Study

Author

Devic, Guillaume, Sassatelli, Gilles, Gamatié, Abdoulaye, ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), This work has been supported by the CONTINUUM ANR project under the grant number ANR-15-CE25- 0007-01, and the R&D ARPE-CONTINUUM project funded by Région Occitanie (France)., ANR-15-CE25-0007,CONTINUUM,Continuum de Conception pour Noeuds de Calculs Energétiquement-Efficaces de Prochaine Génération(2015), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Gamatié, Abdoulaye, and Continuum de Conception pour Noeuds de Calculs Energétiquement-Efficaces de Prochaine Génération - - CONTINUUM2015 - ANR-15-CE25-0007 - AAPG2015 - VALID

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Energy-efficiency, Embedded systems, [INFO.INFO-SE] Computer Science [cs]/Software Engineering [cs.SE], Machine learning, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Edge computing, Heterogeneous architecture, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], FPGA, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems
Abstract

International audience; This paper presents a case study on the combination of a few static code optimization with an FPGA prototype of heterogeneous multicore architecture to address the energy-efficient execution of machine learning algorithms at the edge computing nodes. Two kinds of optimizations are applied : usual compiler optimizations and real number representations (fixed-point versus floating-point). This study is conducted while accounting for the trade-off between training precision, performance, and energy.

Published
2020

38. Deliverable D4.2 – Preliminary design specifications of the adaptive compute node

Author

Bernabovi, Stefano, Chapman, Michael, Naudin, Philippe, Devic, Guillaume, Gamatié, Abdoulaye, Sassatelli, Gilles, Cortus S.A. [Montpellier], ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Cortus S.A.S, LIRMM (UM, CNRS), and ANR-15-CE25-0007,CONTINUUM,Continuum de Conception pour Noeuds de Calculs Energétiquement-Efficaces de Prochaine Génération(2015)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]
Abstract

Every effort has been made to ensure that all statements and information contained herein are accurate, however the Continuum Project Partners accept no liability for any error or omission in the same.

Published
2019

39. Deliverable D5.1 – Technical description of the holistic design flow in CONTINUUM

Author

Bouziane, Rabab, Rohou, Erven, Bruguier, Florent, Devic, Guillaume, Gamatié, Abdoulaye, Leobas, Guilherme, Novaes, Marcelo, Novo, David, Péneau, Pierre-Yves, Quintão Pereira, Fernando Magno, Sassatelli, Gilles, Bernabovi, Stefano, Chapman, Michael, Naudin, Philippe, Pushing Architecture and Compilation for Application Performance (PACAP), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes 1 (UR1), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Cortus S.A. [Montpellier], LIRMM (UM, CNRS), Cortus S.A.S, ANR-15-CE25-0007,CONTINUUM,Continuum de Conception pour Noeuds de Calculs Energétiquement-Efficaces de Prochaine Génération(2015), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), and Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE]
Abstract

The CONTINUUM project aims to define a new energy-efficient compute node model, which will benefit from a suitable combination of efficient compilation techniques, emerging memory, and communication technologies together with heterogeneous cores. This deliverable provides a technical summary of the different studies that contribute to the holistic design flow of CONTINUUM: energy consumption optimization through innovative compilation approaches and cache memory system design, taking into account the integration of non-volatile memory technologies; a workload management technique enabling performance and energy improvements in heterogeneous multicore systems; and finally, the compute node architecture prototype designed with the Cortus core technology.

Published
2019

44. High Performance SoC Design Using Magnetic Logic and Memory

Author

Zhao, Weisheng, primary, Torres, Lionel, additional, Cargnini, Luís Vitório, additional, Brum, Raphael Martins, additional, Zhang, Yue, additional, Guillemenet, Yoann, additional, Sassatelli, Gilles, additional, Lakys, Yahya, additional, Klein, Jacques-Olivier, additional, Etiemble, Daniel, additional, Ravelosona, Dafiné, additional, and Chappert, Claude, additional

Published
2012
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47. Energy-Efficiency Metric for Real-Time Monitoring of OpenMP Programs Executing on Multicore Systems

Author

Mirka, Maxime, Sassatelli, Gilles, Gamatié, Abdoulaye, ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[SPI]Engineering Sciences [physics], [INFO]Computer Science [cs]
Abstract

International audience; Energy-efficiency has been a major challenge in compute systems over the last decade. In this paper, we propose an approach for on-line energy-efficiency mesurement when executing OpenMP workloads on multicore systems. The novelty of our approach lies in the ability to monitor energy efficiency at run-time without prior knowledge of the application profile or code annotation. The solution relies on two new metrics: the Chunks per Second (CpS) and Chunks per Joule (CpJ). The former captures the quantity of work achieved by threads per unit time (i.e. a performance indicator). The latter indicates the quantity of work achieved by threads per unit energy, also corresponding to the performance per watt. We show that these new metrics are suitable information making it possible to perform energy efficiency analysis.

Published
2019

48. Design Exploration Framework for 3D-NoC Multicore Systems under Process Variability at RTL level

Author

Effiong, Charles, Gamatié, Abdoulaye, Sassatelli, Gilles, ADAptive Computing (ADAC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), and LIRMM (UM, CNRS)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Multicore Systems, Simulation Framework, Three-Dimensional Network-on-Chip, Defective TSV, Hardware_INTEGRATEDCIRCUITS, Process Variability, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Hardware_PERFORMANCEANDRELIABILITY
Abstract

This paper presents an RTL design and evaluation framework allowing the designer to easily build and analyze 3D NoC models with customizable defect threshold on Through-Silicon-Via (TSV) vertical links. The framework provides enough flexibility for addressing 3D NoC design issues, such as process variability, which can introduce open-resistive TSVs in the design, caused by impurities and/or defect during manufacturing process. Such TSVs lead to slower data transfers compared to non defective TSVs. To illustrate the usage of the framework usage, we evaluate typical application mappings in a 3D NoC multicore system to mitigate the performance penalty related to process variability.

Published
2018

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