34 results on '"Scheer, Patrick"'
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2. Modelling and analysis of gate leakage current and its wafer level variability in advanced FD-SOI MOSFETs
3. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements
4. Resistive Feedback LNA design using a 7-parameter design-oriented model for advanced technologies
5. Static and LFN/RTN Local and Global Variability Analysis Using an Addressable Array Test Structure
6. Design-oriented model for short-channel MOS transistors based on inversion charge
7. Corrections to “Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge”
8. Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge
9. Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET
10. SOI CMOS and SiGe BiCMOS Technologies for RF and mmW Applications
11. Influence of Calibration Methods and RF Probes on the RF Characterization of 28FD-SOI MOSFET
12. Reliable Technology Evaluation of SiGe HBTs and MOSFETs: fMAXEstimation From Measured Data
13. L-UTSOI: A compact model for low-power analog and digital applications in FDSOI technology
14. In-wafer variability in FD-SOI MOSFETs: detailed analysis and statistical modelling
15. RF Characterization of 28 nm FD-SOI Transistors Up to 220 GHz
16. Transadmittance Efficiency Under NQS Operation in Asymmetric Double Gate FDSOI MOSFET
17. Characterization Methodology and Physical Compact Modeling of in-Wafer Global and Local Variability
18. Reliable Technology Evaluation of SiGe HBTs and MOSFETs: fMAX Estimation From Measured Data.
19. Experimental ${g}_{m}/{I}_{{D}}$ Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET
20. Sensitivity analysis of C-V global variability for 28 nm FD-SOI
21. Systematic evaluation of the split C-V based parameter extraction methodologies for 28 nm FD-SOI
22. Analog and RF modeling of FDSOI UTBB MOSFET using Leti-UTSOI model
23. Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description
24. Experimental gm/{I}{D} Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET.
25. Revisited RF Compact Model of Gate Resistance Suitable for High- $K$/Metal Gate Technology
26. Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses
27. Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET
28. Aging of 40nm MOSFET RF parameters under RF conditions from characterization to compact modeling for RF design
29. CARbridge , reduction of system complexity by standardisation of the system-basis-chips for automotive applications
30. Hicum and BSIM3V3.2.4 non linear behavior validation In RF BICMOS SiGeC 0.25µm process for bipolar and CMOS transistors
31. Is SOI CMOS A Promising Technology For SOCs In High Frequency Range ?
32. Revisited RF Compact Model of Gate Resistance Suitable for High- K/Metal Gate Technology.
33. Experimental g(m)/I-D Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET
34. Wide band and noise characterization of various MOSFETs for optimized use in RF circuits
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