Search

This study examines whether sell-side analysts fully incorporate into their earnings forecasts the joint effects between accounting conservatism and changes in real investment on the quality of current earnings. Our results indicate that sell-side analysts do not fully incorporate such effects when they forecast future earnings so that they overestimate (underestimate) future earnings when current earnings are inflated (depressed) by those effects. Thus, we conclude that sell-side analysts do not recognize fully the joint effects between accounting conservatism and real activity on the earnings quality and that they need to mitigate their bias to enhance market efficiency by providing investors with a good benchmark for their earnings expectation.

Very Large Scale Integrated chip design consists of several steps including modeling characteristics of transistors, profiling circuit level behaviors, abstracting into gate level parameters, synthesizing logic based on timing constraints, and so on. The common concept that runs through all these sequence of design flow is modeling. Traditional VLSI design highly replies on the modeling process, and the percentage that a design chip is successful, or say yield, is determined by how much the modeling is done accurately and precisely. In order to increase the yield, designers put margins while they design. A designer assumes worst cases in design parameters like transistor speed, supply voltage, temperature, and operation frequency. Even though sufficient margin on those design parameters leads higher chance of success in chip design, the margins imply overhead on the other hand. The overhead costs additional power consumption, which should be conquered in this lowpower era. Another cause of such over-design is variable workload in a system. Most of traditional VLSI systems are designed to support the maximum possible workload and the system becomes to have headroom in terms of performance when the workload is not that high. Modern VLSI designs deploy the concept of adaptive control schemes to manage the costs caused by the over-designs. A chip embeds transistor speed meter, and temperature sensors to monitor actual environment that the chip is operating in, and adjusts the margins to be minimal in order to minimize the additional cost. According to the workload offered to the system, the system controls its supply voltage dynamically thus the system keeps its performance just as enough. In this chapter, we introduce the design cases that use adaptive control schemes to manage the overhead while reducing power consumption. One another factor causing over-design is uncertainty, which is emerged in recent VLSI design area. Huge complexity of system-on-chips and ever shrinking transistor size has brought the uncertainty issue in modern VLSI design. One example is clock synchronization issue. As the clock frequency goes beyond Giga-hertz, the chip area is no longer bounded within a single clock cycle, thus, clock synchronization in a chip became extremely challenging, and even impossible to achieve. The terminology, Network-on-Chip has begun to widely spread in the VLSI design field as a chip becomes a set of systems interconnected through a network. In such a big system, transmitting and receiving data signals involves timing uncertainty because it is no longer a synchronous system. Such uncertainty incurs

A structured packet-switched networks-on-chip (NoC) is designed and implemented for high-performance heterogeneous SoC design platform. The chip integrates multiprocessors, multiple memories, and other heterogeneous intellectual properties and interconnection with 51mW and 1.6GHz on-chip networks. The NoC adopts a partial activated crossbar, low-energy coding, and low-swing signaling for the power consumption optimization. A network-in-package integrating four NoCs is fabricated in a 676-BGA-type package for larger and scalable systems and demonstrates 2D-image-processing and 3D-graphics applications

An adaptive network-on-chip (NoC) is implemented with self-calibration and dynamic bandwidth control. The chip calibrates skew between clock domains automatically for reliable mesochronous communication. Link bandwidth is controlled adaptively according to network traffic for energy-efficient packet transmission. A new on-chip serialization scheme, wave-front train (WAFT), is used in the NoC chip to realize high-performance serial link with minimum overhead. The chip is fabricated using 0.18/spl mu/m CMOS technology. The overall network and WAFT operations are successfully measured at 1.2Gb/s and 3Gb/s, respectively.

A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.

A 10.8/spl times/6.0mm/sup 2/ prototype chip is implemented with a star-connected on-chip network. The chip consists of a PLL, 1KB SRAM, two 2/spl times/2 crossbar switches, Up/Down-Samplers, two off-chip gateways, and synchronizers. The on-chip network contains 81k transistors, dissipates 264mW at 2.3V and 800MHz, and provides 1.6GB/s per port and 12.8GB/s aggregated bandwidth, supporting plesiochronous communication without global synchronization.

We implement a rendering engine which has 7.1 GB/s bandwidth and 11.1 Mpolygon/s drawing speed. It has 3D rendering functions such as double buffering, smooth shading, alpha blending and depth comparison. It can convert 3D primitives into complete pixel data in every 90 ns. A serial access memory permits simultaneous memory access both for rendering operation and for screen refresh operation. The proposed virtual page mapping performs rendering operation without a page miss irrespective of the location of a polygon in the screen. Also, the partial word line activation and the sequential block activation can reduce the power consumption of 64 concurrent memory arrays to only 1.2 W.

In this paper, a high-speed 64-bit carry look-ahead adder is implemented by race logic for fast carry generation. G/sup 1/g/G/sup 1/k (Level 1 Group Generate/Kill) and G/sup 2/g/G/sup 2/k (Level 2 Group Generate/Kill) stages are designed by race logic. The adder consists of 4-stages, and clk-S63 delay is 480 ps with 0.18 /spl mu/m CMOS technology.

An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.

A 16.3 mW low power motion compensation (MC) block IP with 1.25 Mbit embedded DRAM macro is implemented using 0.18 /spl mu/m EML technology for portable video applications. For low power consumption, its frequency is lowered to 20 MHz by utilizing parallelism in datapath. Embedded DRAM frame buffer eliminates external data I/O. In addition, distributed nine-tiled mapping (DNTM) with partial activation scheme reduces power for accessing the frame buffer up to 31% compared to conventional 1-bank tiled mapping. Adaptive fetch control (AFC) in data buffer reduces power up to 29% by eliminating unnecessary switching in datapath.

A dedicated single-chip multilevel parallel graphics cache memory for high-speed parallel texture mapping in PC graphics has been fabricated by a 0.16 /spl mu/m DRAM technology. The proposed cache architecture is composed of four components: 1) an 8 MB DRAM L2 cache, 2) eight 16 KB SRAM L1 parallel caches, 3) eight pipelined texture data filters, 4) serial-to-parallel latches. The refill bandwidth of the parallel L1 cache is maximized up to 75 GB/sec by a hidden double data transfer scheme between the L2 and L1 caches. Furthermore, by adaptive sub-wordline activation scheme, the line sizes of the L2 and L1 caches are reconfigurable for achieving optimal cache miss rate and lower power consumption. The SRAM L1 caches and the texture filters by use of parallel pipelined structures result in higher system performance.

Embedded memory logic (EML) is already studied for a possible solution to the system on a chip. Several different architectures are reported for maximal utilization of memory bandwidth between processor and memory. The one-dimensional processor and memory array has been applied to image processing or 2D graphics. Two-dimensional array architecture, however, is well matched to 3D graphic rendering application because basic primitives of 3D graphics such as triangles or rectangles have 2-dimensional spatial locality on the screen and they can be concurrently processed using a 2-dimensional array architecture. This 3D graphic rendering engine based on the 2D array embedded memory logic has 8 edge processors (EP), 64 pixel processors (PP), 64 frame buffers (FB) and 64 serial access memories (SAM) on the same chip. Its 3D operations include the Gouraud shading, alpha blending, depth comparison and double buffering.