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The general goal of this work is to demonstrate that the buried defect layer created by hydrogen implantation can serve as a gettering region for hydrogen introduced from a DC plasma and to study the efficiency of this gettering affected by the implantation regimes. Standard n-type 4.5 Ω x cm Cz Si wafers were implanted by hydrogen ions with an energy of 100 keV and different doses of 1 x [10.sup.14], 1 x [10.sup.15], or 5 x [10.sup.15] atoms/[cm.sup.2] at temperatures of 150, 300, 400, or 500°C. After implantation, hydrogen was introduced to the wafers from the DC plasma at 150°C. For a comparative estimation of the hydrogen concentration in the wafers implanted in different regimes Raman spectroscopy was used. The peaks of the Raman spectra associated with molecular hydrogen ([H.sub.2]), vacancy-hydrogen (V-H), and silicon-hydrogen (Si-H) complexes were studied depending on the implantation conditions. It is demonstrated that peaks of Raman spectra depend significantly on the dose and temperature of implantation. This means that the concentration of hydrogen in the wafers could be determined from the concentration and type of defects formed by hydrogen implantation. Maximum peaks associated with [H.sub.2], Si-H, and V-H complexes were observed for the samples implanted at a temperature of 500°C. PACS Nos: 42.55, 42.65 Le but de ce travail est de montrer qu'un defaut cristallin profond cause par l'implantation d'hydrogene peut servir de piege a gaz pour de l'hydrogene introduit par un plasma DC et pour etudier l'efficacite de ce piegeage selon le regime d'implantation. Sur des gaufrettes (wafers) de Cz Si standard de type n de 4,5 Ω x cm, nous implantons des ions hydrogene de 100 keV a differentes doses : 1 x [10.sup.14], 1 x [10.sup.15] ou 5 x [10.sup.15] atom/[cm.sup.2], a des temperatures de 150, 300, 400 ou 500°C. Apres l'implantation, de l'hydroge'ne est introduit dans le Si a partie d'un plasma a 150°C. La dose d'hydrogene introduite pour chaque echantillon etait 5 x [10.sup.16] atom/[cm.sup.2]. Nous utilisons la spectroscopie Raman pour estimer la concentration d'hydrogene introduit dans le Si. Nous avons etudie l'intensite des lignes Raman associees aux complexes hydrogene moleculaire, hydrogene-lacune et silicium-hydrogene en fonction des conditions d'implantation. Nous observons que l'intensite du signal dans les spectres Raman depend significativement des doses et de la temperature d'implantation. Ceci signifie que la concentration d'hydrogene introduit dans le Si est determinee par le type de defaut forme par l'implantation. Le maximum des lignes associees a [H.sub.2], Si-H et L-H a ete observe pour les echantillons implantes a 500°C. [Traduit par la Redaction], Introduction At the present time Smart-Cut® technology [1] based on splitting of thin silicon layer by hydrogen implantation into a wafer is used extensively to produce silicon-on-insulator structures. When silicon [...]

Solar silicon wafers are mainly produced through multiwire-sawing. This sawing implies microcracks on the wafer surface, which are responsible for brittle fracture. In order to reduce the sawing-induced cracks, the wafers are damage etched after sawing. This paper develops a model for the impact of crack length manipulation on fracture stress distribution. It investigates the effect of damage-etching on the mechanical properties of solar silicon wafers. The main idea is to transform the fracture stress distribution into a crack length intensity function and to model the effect of etching in terms of crack lengths. The fracture stress distribution is determined statistically by fracture tests of wire-sawn and sawn and etched wafers. The Griffith criterion then enables the transition to crack lengths and crack length intensity functions. Two numerical parameters, called truncation parameter and scaling parameter, determine this relationship and enable a quantitative description of the effect of etching. They turn out to be dependent on etchant and geometry of load and thus tested crack population. [DOI: 10.1115/1.3028048] Keywords: fracture theory, fracture stress, etching, silicon wafer, strength, Weibull distribution

Micromachining of (111) silicon wafers by means of a plasma hydrogenation and chemical etching sequence is achieved. Vertical etching is used to define the depth of the craters as well as the thickness of the final suspended silicon body. After protecting the 3-D structure by a thermally grown oxide, a hydrogenation step is used to remove the oxide layer from the bottom of the crater, allowing a lateral underetching. Final exposure of the processed silicon to a KOH solution, etches silicon in a lateral fashion and in the exposed places. A lateral aspect ratio of four to six has been achieved. The evolution of suspended structures on (111) wafers, suitable for sensor fabrication, is feasible without a need to a 3-D lithography. Using this technique suspended inter-digital structures have been realized with a depth up to 70 [micro]m. In addition, ultrathin fully suspended structures have been successfully fabricated. A preliminary capacitive accelerometer has been realized and tested on (111) substrate. [2008-0070] Index Terms--Chemical etching, hydrogenation, micromachining, (111) wafers.

Various publications address the suppression of the undesired mode coupling in laterally bounded conductor-backed coplanar waveguides (CPWs). In this paper, we present an integrated waveguide structure in which this coupling effect of different guided modes is deliberately exploited. Efficient forward coupling at arbitrary levels is achieved between a substrate integrated rectangular waveguide (SIW) and a CPW on its broad wall. Such hybrid integrated couplers combine the SIW's low-loss property with the CPW's flexibility and monolithic microwave integrated circuit compatibility. They are attractive for transitions, six-ports, antenna feeding networks, active antennas, and distributed phase shifters or amplifiers in millimeter-wave applications. The coupling mechanism is studied and a rapid design becomes feasible by use of the provided theory. Two couplers (a 3- and 0-dB version with 4.95- and 9.8-mm-long coupling sections) were designed and fabricated on alumina substrate for operation around 50 GHz. The 3-dB coupler achieves a wide relative bandwidth of 25% at 0.5-dB amplitude imbalance due to the asymmetric coupling structure, whereas the 0-dB coupler (transition) has a 7 % relative bandwidth at less than -0.2-dB coupling loss. Results obtained from millimeter-wave probe measurements on realized prototypes agree well with our theory and simulations. Index Terms--Coplanar wavegnides (CPWs), coupled-mode analysis, millimeter-wave couplers, substrate integrated circuits (SICs), substrate integrated waveguides (SIWs).

In this paper, an active guarding circuit is presented for wideband substrate noise suppression. A feed-forward compensation mechanism is proposed to extend the noise suppression bandwidth and to adjust the amplitude of phase-inversed noise cancellation current by introducing a zero and an amplitude controller. A noise decoupling mechanism is developed to provide a decoupling path and to sense the noise level for generating noise cancellation current. With substrate characterization, parameters of substrate network impedance, decoupling factor, and amplitude of noise cancellation current can be either obtained or determined. The active guarding circuit is implemented in a 90-nm CMOS process based on substrate characterization. The measured substrate noise suppression is better than -9 dB from dc to 250 MHz. The -3-dB suppression bandwidth is effectively extended to 1.2 GHz. The power consumption and circuit area are 2.5 mW and 20 [micro]m x 41 [micro]m, respectively. Index Terms--Analog circuits, CMOS integrated circuits (ICs), substrate coupling noise, substrate crosstalk, substrate isolation.

In this paper, we present the development of active liquid aspiration and dispensing units designed for vertical, as well as lateral, liquid aspiration. The devices are based on a single-use thermally expanding polydimethylsiloxane (PDMS) composite, which allows altering its surface topography by means of individually addressable integrated heaters. Devices are designed in order to create an enclosed cavity in the system, due to locally expanding the initially unstructured composite. This enables negative volume displacement and leads to the event of liquid aspiration. To enable this device functionality, two different techniques of selectively creating permanent PDMS bonds have been developed. One approach utilizes the plasma-assisted PDMS bonding technique, together with a patterned antistiction layer to form reversibly, as well as irreversibly, bonded regions. Another approach utilizes microcontact printing of PDMS curing agent, which serves as a patterned intermediate layer for adhesive bonding. Fabricated prototype devices successfully demonstrated the aspiration and release of liquid volumes ranging from 28 to 815 nL. The devices are entirely fabricated from low-cost materials, using wafer-level processes only and do not require external means for liquid actuation. [2007-0113] Index Terms--Fabrication, fluidics, micropumps, wafer-scale integration.

The Hough transformation employing a normal line-to-point parameterization is widely applied in digital image processing for feature detection. In this paper, we demonstrate how this same transformation can be adapted to classify defect signatures on semiconductor wafers as an aid to visual defect metrology. Given a rectilinear grid of die centers on a wafer, we demonstrate an efficient and effective procedure for classifying defect clusters composed of lines at angles of 0[degrees], 45[degrees], 90[degrees], and 135[degrees] from the horizontal, as well as adjacent compositions of such lines. Included are defect clusters representing stripes, scratches at arbitrary angles, and center and edge defects. The principle advantage of the procedure over current industrial practice is that it can be fully automated to screen wafers for further engineering analysis. Index Terms--Defect metrology, Hough transformation, image processing, process control, spatial defect analysis and classification, wafer maps.

This paper reports a MEMS vacuum package with vertical feedthroughs formed in a glass substrate all at the wafer level. This approach satisfies requirements for MEMS vacuum packages, including small size, vacuum/hermetic capability, sealed and low parasitic feedthroughs, wafer-level processing, compatibility with most MEMS processes, and low cost. It also enables flip-chip solder attachment to a PC board. The package has an integrated micro-Pirani gauge on a glass substrate for in situ monitoring, a silicon cap, and vertical feedthroughs through the glass. The integrated Pirani gauge has 0.6 milli-torr resolution at 0.1 torr and 0.2 torr resolution at 100 torr. Using the Pirani gauge, the fabricated vacuum package is characterized. The package has maintained ~33 torr base pressure with [+ or -]1.5 torr uncertainty for more than four months without a getter. The long-term measured pressure uncertainty is from the measurement setup and environment, and can be improved using a getter inside the package. [2007-0160] Index Terms--Package, Pirani, vacuum, vertical feedthrough.

A practically modified ATR configuration has been proposed for in situ electrochemical surface-enhanced IR absorption spectroscopy (SEIRAS) by sandwiching an ultrathin water interlayer between a hemicylindrical ZnSe prism and a Si wafer as an integrated window. This new ATR optics significantly enhances the throughput of an effective IR beam across the ZnSe/gap/Si/metal film, enabling high-quality spectral fingerprints down to 700 [cm.sup.-1] to be readily detected at larger incidence angles without compromising the electrochemical feasibility and stability of metallic films deposited on Si. The advantages of this modified ATR-SEIRAS have been initially applied to explore two selected systems: wide-ranged in situ ATR-SEIRA spectra provided strong evidence in support of the formate intermediate pathway for methanol electrooxidation at the Pt electrode in an acid solution; in addition, new spectral fingerprints revealed comprehensive orientational information about of the p-nitrobenzoate species at Pt electrode as a result of the dissociative adsorption of p-nitrobenzoic acid molecules from an acid solution.

The paper deals with the new 3-D structures fabricated by the bulk micromachining of (110), (112), and (522) silicon substrates. The structures employ a specific arrangement of {111} planes on these substrates and are entirely bounded by these slowly etching planes. Design rules and complete structures of new seismic-mass systems, suspended on two or four beams, composed of the {111} planes, are presented. The beams supporting the masses are inclined toward the substrate at different angles, which can be adjusted by an appropriate selection of crystallographic orientation of the etched substrate. The structures seem to be interesting as structural components of multiaxes accelerometers. Slanted membranes fabricated by the double-sided etching of (112) and (552) substrates have also been presented. The structures utilize the {111} planes, inclined at a low angle toward the etched substrate, both as structural elements, as well as a natural etch stop. It can be claimed that the application of Si substrates with unconventional crystallographic orientations opens new possibilities in the micromachining of 3-D structures. [2007-0116] Index Terms--Bulk micromachining, membranes, seismic-mass systems, silicon, (hkl) substrates.

In this paper we propose spatial modeling approaches for clustered defects observed using an Integrated Circuit (IC) wafer map. We use the spatial location of each IC chip on the wafer as a covariate for the corresponding defect count listed in the wafer map. Our models are based on a Poisson regression, a negative binomial regression, and Zero-Inflated Poisson (ZIP) regression. Analysis results indicate that yield prediction can be greatly improved by capturing the spatial distribution of defects across the wafer map. In particular, the ZIP model with spatial covariates shows considerable promise as a yield model since it additionally models zero-defective chips. The modeling procedures are tested using a practical example. Keywords: Generalized linear models, negative binomial regression, spatial clustering, wafer map, yield, zero-inflated Poisson regression, 1. Introduction Integrated circuit (IC) processes and production equipment have undergone tremendous changes over time, fostering rapid technological advances throughout the industry. The semiconductor industry has been able to double [...]

The examination of cobalt salicide-induced static random access memory (SRAM) leakage in 90-nm technology is discussed. Findings reveal that the abnormal SRAM leakage originated from junction leakages and resulted in high direct-drain quiescent current and low function yield at wafer level.

A new general 4-port algorithm for on-wafer transistor measurements is presented. Findings reveal that the solved 4-port network for on-wafer parasitics is reciprocal.

The novel RF-split-C-V method is used for the extraction of effective channel length. Findings reveal the observation of a universal behavior identical to the classical long-channel one in the extracted short-channel mobility.

A modified pseudoMOSFET technique is used to reproducibly characterize the quality of the buried oxide (BOX) interface of silicon-on-insulator (SOI) wafers. Findings reveal that the technique is useful for avoiding the problems of different mechanical probe forces and the degeneration of the drain current due to decreasing surface quality.

The purpose of this paper is to address the issues of deembedding multigigahertz CMOS measurements by extensively comparing six popular methods and by proposing a new method based on two-port measurements. The comparison aims to evaluate the maximum applicable frequency of equivalent-circuit methods (open-short, three step, ... ) and the effect of the source dangling leg of MOSFETs on the cascade methods (two line and thru). Fifty dummy structures and 12 MOSFETs were fabricated using standard 0.18-[micro]m CMOS technology. It was found that, at low frequencies ( Index Terms--Deembedding methods, four step, improved three step, on-wafer measurements, open-short, three step, thru, thru-short, two line.

A portable ellipsometer with a compact static polarimeter using an arrayed polarizer, an arrayed wave plate, and a CCD image sensor is developed. A high level of repeatability at a measurement speed of 0.3 s is demonstrated by measurement of Si[Q.sub.2] films ranging from 2 to 300 nm in thickness deposited on an Si wafer. There is the potential to realize an ultracompact ellipsometer module by integrating the optical source and receiver, suitable for deployment in a variety of manufacturing equipment and measurement instruments. OCIS codes: 120.2130, 120.5410.

Multichip integration provides an attractive means to overcome space limitations for large-port-count optical microelectromechanical systems (MEMS) routing systems by allowing actuation and control wiring to be fabricated separately on one chip and then attached beneath a second chip that is populated with a densely packed mirror array. In such systems, vertical as well as horizontal chip alignment is critical when a large but very uniform separation must be maintained across the extent of the array. A technique for creating a structure that simultaneously provides accurate large-gap spacing and acts as a chip-bonding agent is presented here. Specialized processing of an 80-[micro]m-thick photoimaged polyimide structure for bonding mirror and electrode chips for a 1296-mirror array is described, along with measurements of height uniformity within +/- 1% and structure characterization demonstrating suitability for production and long-term stability. The process parameters and simplicity of the technique make it suitable for a wide range of applications where MEMS must be integrated with electronic control circuitry. [2006-0042] Index Terms--Flip-chip devices, optical switches, polyimide films, wafer bonding, wafer-scale integration.

A novel hydrogenation-assisted deep reactive ion etching of silicon is reported. The process uses sequential hydrogen-assisted passivation and plasma etching at low-density plasma powers to stimulate the vertical removal of the exposed Si substrate. The main feature of this technique is the sequential alternation of the electrodes while switching between different gases. Three-dimensional structures with aspect ratios in excess of 40:1 and features as small as 0.7 [micro]m have been realized. The net etch rate is about 0.25 [micro]m/min, although higher rates are expected to be achievable. [2007-0067] Index Terms--Deep reactive ion etching (DRIE), hydrogen plasma, micromachining, silicon wafers, vertical etching.

The design of a magnetically levitated superconducting conveyer for wafer transportation is discussed. Findings reveal that the usage of proportional and differential control suppresses the vibrations of displacement.

A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced in this paper. The process is based on etching cavities in silicon, followed by anodic bonding of a thin glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and due to the expansion of the trapped gas in the silicon cavities the glass is blown into three-dimensional spherical shells. An analytical model which can be used to predict the shape of the glass shells is described and demonstrated to match the experimental data. The ability to blow glass on a wafer level may enable novel capabilities including mass-production of microscopic spherical gas confinement chambers, microlenses, and complex microfluidic networks. [2006-0092] Index Terms--Fabrication, glass, glass blowing, glass bubble, glass shell, microglass sphere, micromachining, spheres, wafer-level manufacturing.

We present in this paper parametric studies of board-level reliability of wafer-level chip-scale packages subjected to a specific pulse-controlled drop test condition. Eighteen experiment cells, constructed by varying joint pitch, die thickness, and die size, are proposed and examined numerically. The transient analysis follows the support excitation scheme and incorporates an implicit time integration solver. Numerical results indicate that the drop reliability of the package enhances as the die thickness as well as the die size decreases. Moreover, the package with smaller solder joints and a smaller joint pitch suffers a greater drop reliability concern. [DOI: 10.1115/1.2429717] Keywords: board-level drop test, WLCSP, reliability, JEDEC

The 1.5 [micro]m CMOS fabrication processes are employed for nano metal-oxide semiconductor field effect transistor (nMOSFET) nonvolatile memory (NVM) devices containing single-layer and doubly stacked Si nanocrystals (NCs) with defect states minimally reduced by using ion beam sputtering deposition (IBSD) under ultrahigh vacuum (UHV). The memory characteristics of the devices, especially prominent retention properties compared to the previously reported data are presented.

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach. Index Terms--Microlithography, photoresist processing, real-time control, semiconductor manufacturing, temperature control.

Warped wafers can affect device performance, reliability, and linewidth control in various processing steps. We propose in this paper an in situ fault detection technique for wafer warpage in lithography. The use of advanced process control results in very small temperature disturbance making it suitable for industrial implementation. Index Terms--Fault detection, lithography, temperature measurement, wafer warpage.

The reliability of imprint patterns molded by stamps for industrial application of nanoimprint lithography (NIL) is an important issue. Usually, defects can be produced by incomplete filling of negative patterns and the shrinkage phenomenon of polymers in conventional NIL. In this paper, the patterns that undergo a varied temperature or varied pressure period during the thermal NIL process have been investigated, with the goal of resolving the shrinkage and defective filling problems of polymers. This paper also studies the effects on the formation of polymer patterns in several profiles of imprint processes. Consequently, it is observed that more precise patterns are formed by varied temperature (VT-NIL) and varied pressure (VP-NIL). The NIL (VT-NIL and VP-NIL) process has a free space compensation effect on the polymers in stamp cavities. From the results of the experiments, the polymer's filling capability can be improved. VT-NIL is merged with the VP-NIL, resulting in a better filling property. The patterns that have been imprinted in merged NIL are compared with the results of conventional NIL. This study achieves improvement in the reliability of the results of thermal NIL. Index Terms--Defect control, free volume compensation, nanoimprint lithography, polymer shrinkage.

Recently, the 3D or stacked-die packages become increasingly popular for packaging ICs into a system or subsystem to satisfy the needs of low cost, small form factor, and high performance. For the applications of these packages, IC silicon wafers have to be ground to be relatively thin through the wafer-thinning processes (such as grinding, polishing, and plasma etching). The strength of dies has to be determined for the design requirement and reliability assurance of the packages. From the published data, there still exist some issues, including a large scatter existed in die strength data and difficulties in differentiating the causes of the low strength between from the wafer grinding and from wafer sawing by either the three-point bending or four-point bending test. The purposes of this study are to develop new, reliable, and simple test methods for determination of die strength, in order to improve the data scatter, and to provide a solution for differentiating the factors that affect the variability of die strength for finding out the causes of the weakness of the die strength. In this study, two new test methods, point-loaded circular plate with simple supports test (PLT-I) and point-loaded plate on elastic foundation test (PLT-II), are proposed and then evaluated by testing two groups of silicon dies with different surface conditions. The surface conditions (roughness) of the specimens are determined by atomic force microscopy and correlated to failure strength. The failure forces from both tests have to be modified by using maximum stress obtained from theories or finite element analyses to obtain the failure strength. The test results are compared to each other and further with a widely used four-point bending test. The results suggest that, unlike the four-point bending test suffering the chipping effect, both methods provide very consistent data with a small scatter for each group of specimens and can be used for identifying the effect of surface grinding (roughness) on the die strength. It is also shown that the die strength is highly dependent on the surface roughness. Accordingly, these two methods can provide not only a (biaxial) stress field similar to temperature-loaded die in the packages, but also simple, feasible, reliable, and chipping-free tests for silicon dies of dummy or real IC chips, without strict geometrical limitation, such as beam-type geometry for the three-point or four-point bending test. [DOI: 10.1115/1.2351907] Keywords: electronic packaging, die strength, test method, failure mode, point loading, four-point bending, wafer thinning

To improve the fidelity of the microinjection molding process, research is underway to implement silicon inserts as tooling surfaces in an injection molding machine. These tooling surfaces are created using typical microfabrication processes, such as bonding and chemical etching. The primary focus of this paper is the evaluation of anistropic wet etching of off-axis silicon wafers, including experimental results and simulations. A method is presented for the determination of the (110) direction and subsequent alignment of the mask with an accuracy of 0.01[degrees]. The use of atomistic kinetic Monte Carlo simulations reveals the extreme importance of proper alignment between the mask features and the off-axis wafer. As an example application, the fabrication steps and corresponding simulations of a silicon insert for the manufacture of disposable plastic razors are presented. Index Terms--Anisotropic etching, atomistic simulation, micromolding, wafer alignment.

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only expensive and time consuming but also it leads to high misidentification levels. In this paper, an automatic approach consisting of a spatial filter, a classification module and an estimation module is proposed to validate both real and simulated data. Experimental results show that three types of typical defect patterns: (i) a linear scratch; (ii) a circular ring; and (iii) an elliptical zone can be successfully extracted and classified. A Gaussian EM algorithm is used to estimate the elliptic and linear patterns, and a spherical-shell algorithm is used to estimate ring patterns. Furthermore, both convex and nonconvex defect patterns can be simultaneously recognized via a hybrid clustering method. The proposed method has the potential to be applied to other industries., 1. Introduction The manufacture of integrated circuits is a complex and costly process that involves hundreds of steps and requires the monitoring of many process parameters throughout the production process. [...]

This paper investigates the sensitivity of on-wafer coupled interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. Some important parameters characterizing the coupled interconnects have been examined. The influence of the process parameters on transmission, reflection, near-end, and far-end crosstalk capacities of the coupled interconnects are discussed. Index Terms--CMOS process, coupled interconnects, sensitivity.

A three-dimensional (3-D) integration technology is developed for the fabrication of a new 3-D shared-memory test chip. Results confirm that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip.

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The three-dimensional intergration process is described as well as the properties of the four enabling technologies.

The impact of diffusion-induced dislocations on the recombination statistics in n-type and -type silicon wafers and the terminal characteristics of high-efficiency double-sided buried contact silicon solar cells made on both types of wafers is explored. The results have shown that n-type silicon wafers are more tolerant to chemical and crystallographic defects and hence they have exceptional potential as a wafer for high-efficiency commercial silicon solar cells.

We describe a simulation study of a production planning model for multistage production inventory systems that reflects the nonlinear relationship between resource utilization and lead time. The model is based on the use of clearing functions that capture the nonlinear relationship between workload and throughput. We show how these clearing functions can be estimated from empirical data using a simulation model as a surrogate for observation of the production system under study. We then examine the sensitivity of the estimated clearing function to different dispatching algorithms, different demand patterns, and production planning techniques. Computational experiments based on a scaled-down model of a semiconductor wafer fabrication facility illustrate the potential benefits of the clearing function model relative to conventional linear programming models. Index Terms--Cycle times, linear programming, production planning, wafer fabrication.

The design and fabrication of high performance high power lasers with emission wavelength from 800 to 1000 nm using a novel wafer structure is described. The suppression or elimination of higher order mode lasing by the structure enhances the laser kink-free power.

The power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures is presented. It is concluded that the small-signal power gain and PAE of SiGe HBT's increase with temperature at low base voltages, when the base voltage is kept with a constant value because the collector current increases with temperature, the cutoff frequency will increase, leading to the increase of power gain.

Recently, a comprehensive model has been developed by Luo and Dornfeld ('Material removal mechanism in chemical mechanical polishing: theory and modeling,' IEEE Trans. Semiconduct. Manufact., vol. 14, pp. 112-133, May 2001) to explain the material removal mechanism in chemical mechanical planarization (CMP). Based on the model, the abrasive size distribution influences the material removal from two aspects, one, the number of active abrasives, and the other, the size of the active abrasives. In this paper, experimental evidence supporting this view of abrasive size effects is discussed. A detailed model of wafer-abrasive-pad contact is developed to explain how and where abrasive size distributions come into the comprehensive material removal model. A material removal rate formulation as a function of abrasive size distribution is proposed and verified. In the future, the application of the model to the CMP process optimization, for example, improving the nonuniformity, or obtaining minimum surface scratching and preferred material removal rate by changing abrasive size distribution, may be attempted. Index Terms--Active abrasive number and size, chemical mechanical planarization, modeling.

The authors propose a new accurate yield prediction method for system-LSI embedded memories to improve the productivity of chips. Their new method is based on the failure-related yield prediction method in which failure bits in memory are tested to see whether they are repairable or not by using built-in redundancies. The important concept of the new method is called 'repairable matrix' (RM). In RM, r[m.sub.ij] = 1 means that i row redundancy sets and j column redundancy sets are needed for repair, where r[m.sub.ij] is an element of the matrix. Here, RM can indicate all the candidate combinations of the number of row and column redundancy sets for repair. The new yield prediction method using RM solves two problems, 'asymmetric repair' and 'link set.' These have a significant effect on accurate yield prediction but have not yet been approached by conventional analytical methods. The calculation of yield by the new method is demonstrated in two kinds of advanced memory devices that have different design rules, failure situations, and redundancy designs. The calculated results are consistent with the actual yield. On average, the difference in accuracy between the new method and conventional analytical methods is about 5%. Index Terms--Embedded memory, failure, redundancy, semiconductor manufacturing, yield prediction.

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 x [10.sup.18] c[m.sup.-3] and the sheet resistance of 13 nm and 700 [ohm]/s. for As and 14 nm and 770 [ohm]/sq for B[F.sub.2] with junction leakage lower than 1 x [10.sup.-16] A//[micro][m.sup.2] at 1.5 V were successfully obtained without wafer slip and warpage problems. Index Terms--Activation, crack, flash !amp annealing (FLA), junction leakage, low resistance, MOSFETs, preamorphization, slip, stress, ultrashallow junction.

New methods for monitoring via and line voiding in metal interconnect structures are described. A focused laser beam injects heat into a structure such as a line or via chain, which may have width considerably smaller than the spot size. Conduction of heat, and therefore temperature under the spot, is a function of via or line integrity. Probing the temperature using laser reflection provides a direct nondestructive measure of via continuity or line voiding. Index Terms--Copper interconnect, damascene copper, via, void.

Silicon wafer bonding technology is becoming one of the key technologies in the silicon-on-insulator (SOI) structure fabrication. However, the high-temperature heat treatment during SOI fabrication is inevitable, and the thermal stress thus induced could have an adverse effect on the device fabricated and the bonding interface. In this work, a finite-element analysis software, ANSYS, is used to study the induced mechanical stresses at the interface during the withdrawal of wafers from a high-temperature furnace. It is found that the type of insulators and the geometric dimension of the devices such as the thickness of the work layer, insulator layer, and the substrate thickness are insignificant contributors to the induced thermal stresses. Although it is expected that the furnace temperature and withdrawal velocity are the key factors in determining the mechanical stresses, for the present bonding strength of wafers via wafer bonding technology, the withdrawal velocity must be less than 100 mm/min, and under such a withdrawal velocity, the furnace temperature is also an insignificant factor with regard to the induced stress. Index Terms--ANSYS, finite-element analysis, mechanical stress, silicon-on-insulator (SOI), wafer bonding.

Within the framework of linearized thermoelasticity theory, the temperature and thermal stresses on the wafer for the rapid thermal processor are solved by using the finite-difference approach and a trapezoidal integration technique, respectively. Although the equations governing the present thermoelastic system are coupled in nature, the temperature can still be obtained independently due to the fact that the coupling term is negligible as a result of the strain rate being extremely small as compared with unity. Based on the maximum shear stress failure criterion, the calculated results show that material failure always occurs at the edge of the wafer at the beginning of cooling processes. Furthermore, the maximum stress control scheme is proved to be more efficient that it can significantly reduce the required cooling time and thermal budgets. Thus, the conventional constant cooling-rate control scheme or linear temperature ramp-down scheme is not appropriate for the rapid thermal processor. Index Terms--Cooling control, rapid thermal processor, thermal stress, transient heat transfer.

Since laser metal cut processing has become a standard technology in the industry, the improvement of cutting metal lines has been an important issue. There has been extensive research focused on the optimization of metal cut structure as well as laser parameters. In this work, a metal pad cut link (or fuse) structure has been studied in comparison with a conventional metal linear cut structure through experimental observations and verified using three-dimensional finite-element modeling. The novel proposed structure improves the laser cut processing reliability. The finite-element analysis shows that the temperature in the aluminum line of the pad cut structure throughout the laser pulse duration is higher than that of the linear cut structure due to the reduced heat diffusion along the line. Consequently, the upper-corner cracking initiates faster and the lower-corner stress of pad structure develops faster at first, but starts to release right after earlier upper-corner cracking. This faster upper-corner cracking and delayed lower-corner cracking indicate a low chance for lower-corner cracking as well as possible low-power processing. Therefore, the pad cut structures have been shown to have a wider relative cut energy process window, which indicates higher reliability of laser processing and may result in higher density laser fuses. Index Terms--Bulge fuse, energy process window, interconnect, laser fuse, laser processing, link, pad cut, yield enhancement.

Feasibility of single-wafer rapid-thermal process as an alternative to the conventional batch-type furnace process is evaluated on a 0.15-[micro]m 128-Mb mask read only memory (MROM) product. Excellent gate oxide integrity and device characteristics are achieved with a single-wafer rapid-thermal process. Superior yield and product reliability by using single-wafer process tool have also been achieved. Shortened process cycle time and better thermal process uniformity by using single-wafer rapid-thermal processing are demonstrated. Index Terms--Integrity, ISSG, mask ROM, single-wafer.

In this paper, we discuss a new technology implemented with all, single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As a result, a very aggressive cycle time (0.25 days/layer) with high yield, in double-polysilicon, sextuple-metal, 0.18-[micro]m LOGIC process has been demonstrated. High-performance devices with excellent reliability are also obtained. A new methodology for detecting parametric errors effectively in the early stages of production is implemented for quick yield ramp up. Index Terms--Cycle time reduction, failure analysis, manufacturing automation, single-wafer process, yield optimization.