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Perovskite‐silicon (Pero‐Si) tandem solar cells have made remarkable progress in recent years, achieving certified cell efficiencies of up to 33.9%. However, accurately measuring the efficiency and current density‐voltage (JV) curves of these devices poses various challenges including the presence of mobile ions within the perovskite absorber that lead to short‐ and long‐term transient effects. Consequently, both the measurement setup and the preconditioning of the device significantly affect measurement results. This study focuses on enhancing the reliability and comparability of JV and other efficiency measurements for Pero‐Si tandem devices through a systematic analysis of the influence of mobile ions, preconditioning and measurement conditions. For the first time, a full opto‐electrical simulation model for Pero‐Si tandem devices is presented in Sentaurus TCAD, which includes the drift‐diffusion of anions and cations and is therefore able to describe short‐ and long‐term transient device effects in state‐of‐the‐art Pero‐Si tandem cells. Experimental validation and evidence are given by comparison to in‐house Pero‐Si tandem cells, as well as Pero‐Si mini modules from Oxford PV. We analyze by simulation and experiment how the cell preconditioning at different preconditioning voltages and times impacts the resulting measured tandem efficiency, as well as impact of JV scan times for the measured hysteresis in Pero‐Si tandem devices. Furthermore, we demonstrate the impact of current‐mismatching conditions on the measured hysteresis of the Pero‐Si tandem device and the need of correct spectral irradiance settings during measurements. We showcase that even a very slight variation in short‐circuit current density (jsc) around the current‐matching point leads to significantly different hysteresis behaviors. With aid of our simulation model, we could attribute this phenomenon to a reverse/forward biasing of the perovskite sub‐cell impacting the ion drift depending on the current‐limiting sub‐cell of the tandem device. Therefore, it is sensible to be aware of the current limiting sub‐cell for the comparison of the hysteresis susceptibility of different Pero‐Si tandem devices. This study strongly underscores the importance of including the preconditioning and measurement conditions when reporting Pero‐Si tandem efficiencies. The findings highlight the urgent need for standardization in the field. [ABSTRACT FROM AUTHOR]

In the proposed work, cylindrical Nanowire Field Effect Transistors (NWFETs) are created for sub-10 nm applications using the charge plasma (CP) principle. In the middle of the transistor, a gate is surrounded by an oxide layer and a channel layer. By enclosing the channel in an oxide layer and surrounding it with a distinctive metal layer with various work functions, the charge-plasma concept is introduced. A detailed discussion of device characteristics, such as electric potential and transfer qualities, are presented. For channel lengths of 35 and 10 nm, measurements of the threshold voltage, drain current, and ION/IOFF ratio are analyzed. Sentaurus Technology Computer Aided Design (TCAD) is used to evaluate and analyze the device. TCAD simulations that incorporate the Lombardi mobility model, Shockley-Read-Hall (SRH) model, Density-Gradient model, and Auger recombination models make it easier to calculate tunneling and recombination. Interestingly, the CP-based NWFET produces twice as much output current as its traditional NWFET. Because of the Schottky junction's larger vertical field, significant improvements include the reduction of lateral coupling between the source and drain field lines, the stabilization of the ION/IOFF ratio, an overall reduction in parasitic leakage, and improved scalability. This work extends to circuit implementation, featuring the development of an Inverter circuit. Performance assessments are conducted, and comparisons are drawn with varying channel lengths and widths, further substantiating the efficacy of the proposed structure. [ABSTRACT FROM AUTHOR]

Perovskite‐based triple‐junction solar cells offer the potential for highly efficient and cost‐effective photovoltaic energy conversion. This article aims to provide a roadmap for the optical properties of perovskite/perovskite/silicon triple‐junction cells. A comprehensive optoelectrical model for the perovskite/perovskite/silicon structure is developed in Sentaurus TCAD. The optical part of the model is validated by measurements of a triple‐junction solar cell. As the electrical characterization is an ongoing process, the electrical properties are assumed to be nonlimiting, which enables us to translate the optical improvement steps into efficiency potentials. A first improvement step lies in adjusting the thicknesses of the perovskite layers to achieve current matching between both perovskite subcells. Using perovskites with bandgaps optimized for planar surfaces, it would be possible to increase the photocurrent density to 13.3 mA cm−2 and the efficiency to 41.9%. It is shown that by implementing a fully textured structure and using the best available materials, a short‐circuit current of 14.1 mA cm−2 and an open‐circuit voltage of 3.48 V with an efficiency of 44.3% are possible assuming idealized electrical properties. This can be regarded as a practical efficiency potential for this kind of triple‐junction technology. [ABSTRACT FROM AUTHOR]

The lower efficiency of a Photoconductive Antenna is a significant bottleneck in using them for several applications. This manuscript presents a solution to improve the photoconductive antenna performance using the nano-dot structures in the electrode's gap. This study analyses the nano-dots' shape, size, and spacing effects on the current pulse and the frequency response of a normal photoconductive antenna. For the analysis, square, hexagonal, and circular shape dots are considered with different sizes and spacing. The optimization study shows that not all combinations enhance photoconductive antenna performance using the above-defined dots. The circular dot photoconductive antenna produces an enhancement of 63.16 and 166.2% in the current pulse amplitude and radiated power, respectively, using different combinations of nano-dot size and gap. The frequency response analysis shows that the circular dot photoconductive antenna produces highest directivity (8.76 dBi) among all the nano-dot geometries. [ABSTRACT FROM AUTHOR]

A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up approach on a highly n-doped silicon substrate. The electrical performance is studied as a function of various epi-structure parameters, including region lengths and doping levels, nanowire diameter, and the impact of the surface states. The results reveal that the optimized structure has a Normally-OFF mode with a threshold voltage higher than 0.8 V and exhibits minimized leakage current, low on-state resistance, and maximized breakdown voltage. To the best of our knowledge, this is the first exhaustive study of GaN-based nanowire transistors, providing valuable insights for the scientific community and contributing to a deeper understanding of the impact of GaN nanowire parameters on device performance.

Tunnel Oxide Passivated Contact (TOPCon) is considered as an immediate successor of Passivated Emitter and Rear Contact (PERC). Rear side full area hole selective passivating contact with front n + diffused emitter on p-type silicon (Si) (p-TOPCon) would be an incremental upgrade from PERC. However, limited studies are present on p-type Si and most of them are on TOPCon with rear full area electron selective contact (n-TOPCon). In this work, we explore the potential of p-TOPCon by incorporating industry relevant material and process parameters in Sentaurus TCAD simulations. These include bulk lifetime (τ b), wafer resistivity (ρ), polysilicon related rear parameters, front emitter sheet resistance (R s h e e t) and its passivation (S f r o n t), and finger width (W f i n g e r). Simulation results are benchmarked against PERC and n-TOPCon. p-TOPCon outperforms PERC and has lower sensitivity to wider range of τ b , ρ , and S f r o n t. Simulation suggests that an efficiency of 23.83% can be achieved for industrially feasible τ b of 5 ms, ρ of 1 Ω -cm, emitter R s h e e t of 132 Ω /sq, and W f i n g e r of 20 μ m for p-TOPCon. Replacement of diffused emitter with n-TOPCon would be ideal after accomplishing above anticipated advancements and in such a scenario, efficiency > 24.4% can be achieved on p-type Si. • Potential of p-TOPCon for industrial application is presented using Sentaurus TCAD. • p-TOPCon is less sensitive to bulk and surface passivation properties than n-TOPCon. • p-TOPCon can offer efficiency up to 23.83% for industry relevant parameters. • Simulations suggest p-TOPCon can be the immediate successor of PERC. • Adoption of n-TOPCon over p-TOPCon further push the efficiency beyond 24.4%. [ABSTRACT FROM AUTHOR]

Small-pixel is one of the development directions of InSb infrared focal plane devices, but it will have a greater impact on the photocurrent response and crosstalk of the device. Therefore, the mesa junction device model, the planar junction device model and the epitaxial device model of the small-pixel InSb infrared focal plane array device are established using Sentaurus TCAD software. The back-incident three-pixel InSb array devices are used to simulate the photocurrent response and crosstalk of the three device models. The results show that the photocurrent response can be increased and the crosstalk can be reduced for the mesa junction device and the planar junction device by reducing device thickness and increasing junction depth, and the photocurrent response and crosstalk can be improved for the epitaxial InSb device by increasing the thickness of absorption layer and selecting an appropriate doping concentration. Considering the influence of process difficulty, it is re-commended to adopt a deep ion implanted planar junction structure or an epitaxial structure with controllable thickness and doping concentration prepared by molecular beam epitaxy.

A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO)are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO). [ABSTRACT FROM AUTHOR]

Perovskite solar cells (PSCs) are a promising area of research among different new generations of photovoltaic technologies. Their manufacturing costs make them appealing in the PV industry compared to their alternatives. Although PSCs offer high efficiency in thin layers, they are still in the development phase. Hence, optimizing the thickness of each of their layers is a challenging research area. In this paper, we investigate the effect of the thickness of each layer on the photoelectric parameters of n-ZnO/p-CH3NH3PbI3/p-NiOx solar cell through various simulations. Using the Sol–Gel method, PSC structure can be formed in different thicknesses. Our aim is to identify a functional connection between those thicknesses and the optimum open-circuit voltage and short-circuit current. Simulation results show that the maximum efficiency is obtained using a perovskite layer thickness of 200 nm, an electronic transport layer (ETL) thickness of 60 nm, and a hole transport layer (HTL) thickness of 20 nm. Furthermore, the output power, fill factor, open-circuit voltage, and short-circuit current of this structure are 18.9 mW/cm2, 76.94%, 1.188 V, and 20.677 mA/cm2, respectively. The maximum open-circuit voltage achieved by a solar cell with perovskite, ETL and HTL layer thicknesses of (200 nm, 60 nm, and 60 nm) is 1.2 V. On the other hand, solar cells with the following thicknesses, 800 nm, 80 nm, and 40 nm, and 600 nm, 80 nm, and 80 nm, achieved a maximum short-circuit current density of 21.46 mA/cm2 and a fill factor of 83.35%. As a result, the maximum value of each of the photoelectric parameters is found in structures of different thicknesses. These encouraging results are another step further in the design and manufacturing journey of PSCs as a promising alternative to silicon PV. [ABSTRACT FROM AUTHOR]

Low‐cost and high‐efficiency tandem solar cells are promising candidates for a future industrial mass production. Nowadays, the passivated emitter and rear cell (PERC) technology makes up the major market share; therefore, it is an attractive option to use the PERC technology as bottom cell concept for a perovskite–silicon tandem device. Long‐term optimization of the PERC technology led to highly efficient, low‐cost, and mature devices. For PERC‐like bottom cells, mainly an adapted front‐side design is needed: Design constrains of a PERC single junction are relaxed to some extent, because such an updated PERC bottom cell only needs to absorb long wavelength photons, transports about half the current and, in a monolithic tandem, lateral transport, and the use of firing‐through local silver contacts is not a mandatory prerequisite. Consequently, to make PERC suitable for tandem application, a systematic reevaluation of the current PERC technology is performed here considering five different front‐side concepts. We investigate locally contacted and full‐area transparent conducting oxide (TCO)‐based interconnection concepts for PERC, as well as the full‐area tunnel oxide passivating contact (TOPCon). Our simulation work elaborates on the advantages and physical constrains of each concept and gives guidelines for the optimization of the phosphorus diffused emitter and front interconnection layers. We conclude that both full‐area and locally contacted front‐side concepts are promising candidates for achieving tandem cell efficiencies of about 30%. In this work we focus on how to make the mainstream silicon solar cell technology – namely the passivated emitter and rear cell (PERC) – suitable as bottom cell in a perovskite‐silicon tandem device. A detailed optical and electrical simulation model incoporating the parasitic absorption losses and (tunneling) transport at the different bottom cell front side concepts (including passivating contact schemes like TOPCon) was elaborated in Sentaurus TCAD which enables to predict the tandem effi-ciency poten-tial of several PERC‐like bottom cells. [ABSTRACT FROM AUTHOR]

The proposed work focuses on the outcomes brought about by the inclusion of Charge Plasma (CP) concept in a cylindrical Nanowire Field Effect Transistor (NWFET) for sub 10 nm. The Gate is surrounded by an oxide layer, which is further surrounded by a channel layer. The concept of charge-plasma is introduced in the channel by surrounding an oxide layer around the channel, and a different work functions metal layer around the oxide. The performance of device parameters like the electric potential and transfer characteristics have been described. Analysis of Threshold Voltage, drain current and ION/IOFF ratio have been carried for 35 nm and 10 nm channel length. Sentaurus Technology Computer Aided Design (TCAD) has been used to evaluate and analyze this device for sub 10 nm. To calculate tunneling and recombination, the TCAD simulates the Lombardi mobility model, Shockley-Read-Hall (SRH), Density Gradient model, and Auger recombination models. This device generates twice times more output current by using the CP-based NWFET as compared to the conventional NWFET. The parasitic leakage has been reduced and the ION/IOFF ratio has been stabilized. Also, the scalability is enhanced, and the Schottky junction's high vertical field lowers the lateral coupling between the source and drain field lines. This can be used to implement in memory devices such as Inverter, 6T SRAM, 8T SRAM in future. [ABSTRACT FROM AUTHOR]

In this work, a 2 − D analytical model of Dielectrically Modulated, Dual Material, Double Gate Junctionless MOSFET (DMDG-JL-MOSFET) based label free biosensor has been proposed to investigate the effect of high-κ gate dielectric materials (TiO2, HfO2, and Al2O3) and cavity length variation on the sensitivity of the biosensor. The model has been validated with data obtained from Sentaurus TCAD simulator. The variation in threshold voltage (Vth), drain current (Id) and ION/IOFF ratio has been used as the sensing metric to estimate the sensitivity of the proposed biosensor. It has been observed that at a cavity length (Lcav) of 25 nm, TiO2 shows 87%, 68% and 52% higher sensitivity than if SiO2 is taken as gate dielectric in case of neutral, positively charged and negatively charged biomolecules respectively. Further, the effectiveness of the proposed DMDG-JL-MOSFET based biosensor is confirmed by benchmarking the sensitivity metric with contemporary architectures of JL-MOSFET based biosensor. We have reported that DMDG-JL-MOSFET exhibits significant increase in sensitivity when compared to other contemporary JL-MOSFET based biosensors, thus making the proposed device an attractive solution for biosensing applications. [ABSTRACT FROM AUTHOR]

To unlock the full potential of perovskite–silicon tandem solar cells with >30% efficiency at presumably low cost, the transparent conductive oxides (TCOs) and metal grid at the front side need to be adapted compared to classical silicon heterojunction (SHJ) solar cells. By means of optical and electrical modelling, we consider the main aspects to optimize the front electrode for the tandem case, where in contrast to silicon single junction devices, there are (i) different optical properties including a lower refractive index of the perovskite absorber (ii) about half the current, thus quarter the resistive power losses for the same series resistance contribution (iii) lateral transport at the front needs to be provided solely by the front TCO layer and (iv) lower thermal stability of the perovskite, which affects TCO deposition conditions and results in a less efficient sintering of the silver screen printing pastes. This study concludes that compared to silicon heterojunction cells, the thickness of the front TCO should be reduced from 75 nm to around 20 nm, resulting in less parasitic absorption and a potential cost reduction of 1.46 €ct/cell for ITO. We investigate the impact of different front metallization including plating and silver screen printing and showcase that for multi‐wire interconnection concepts, the number of wires can be reduced from 18 wires to 9 or even less depending on the front metallization. Finally, we give an outlook on the silver consumption and levelized cost of electricity. [ABSTRACT FROM AUTHOR]

Ag/ITO/MoOx/n-Si/LiFx/Al carrier-selective contact (CSC) solar cell structures are modelled and numerically simulated based on the experimental data using an industrial quality base silicon wafer by the Sentaurus TCAD software. The role of (1) electron-selective lithium fluoride (LiFx) layer and its thickness, (2) hole-selective molybdenum oxide (MoOx) work function variation, and (3) front contact (MoOx/n-Si) surface passivation interlayer are explored on the device performance. The electron-selective LiFx layer at the rear side is led to the substantial enhancement in device photocurrent by providing the electrical barrier to the minority carriers (holes) and a slight improvement in open-circuit voltage, but the thickness of the layer is sensitive to efficient extraction of the majority carriers (electrons). The hole-selective MoOx layer work function needs to be engineered for inducing the strong inversion layer with better built-in potential at the MoOx/n-Si junction to achieve high open-circuit voltage from a cell. A thin SiOx interlayer at the MoOx/n-Si junction has significantly enhanced the device's open-circuit voltage by minimizing the minority carrier recombination at the interface. [ABSTRACT FROM AUTHOR]

Perovskite solar cells (PSCs) are a promising area of research among different new generations of photovoltaic technologies. Their manufacturing costs make them appealing in the PV industry compared to their alternatives. Although PSCs offer high efficiency in thin layers, they are still in the development phase. Hence, optimizing the thickness of each of their layers is a challenging research area. In this paper, we investigate the effect of the thickness of each layer on the photoelectric parameters of n-ZnO/p-CH3NH3PbI3/p-NiOx solar cell through various simulations. Using the Sol–Gel method, PSC structure can be formed in different thicknesses. Our aim is to identify a functional connection between those thicknesses and the optimum open-circuit voltage and short-circuit current. Simulation results show that the maximum efficiency is obtained using a perovskite layer thickness of 200 nm, an electronic transport layer (ETL) thickness of 60 nm, and a hole transport layer (HTL) thickness of 20 nm. Furthermore, the output power, fill factor, open-circuit voltage, and short-circuit current of this structure are 18.9 mW/cm2, 76.94%, 1.188 V, and 20.677 mA/cm2, respectively. The maximum open-circuit voltage achieved by a solar cell with perovskite, ETL and HTL layer thicknesses of (200 nm, 60 nm, and 60 nm) is 1.2 V. On the other hand, solar cells with the following thicknesses, 800 nm, 80 nm, and 40 nm, and 600 nm, 80 nm, and 80 nm, achieved a maximum short-circuit current density of 21.46 mA/cm2 and a fill factor of 83.35%. As a result, the maximum value of each of the photoelectric parameters is found in structures of different thicknesses. These encouraging results are another step further in the design and manufacturing journey of PSCs as a promising alternative to silicon PV.

Perovskite–silicon tandem solar cells have shown a rapid progress within the past 5 years in terms of their research cell efficiency and are currently being investigated as candidates for the next generation of industrial PV devices. This raises the question of which silicon bottom cell will be most suitable for tandem application. Currently, the silicon heterojunction (SHJ) technology dominates in tandem research achieving world records. However, it is an open issue of how to transfer these research results to industrial mass production, which is driven by cost reduction and resource efficiency and includes challenges like upscaling and long‐term stability. Therefore, it is highly relevant for the PV industry to get reliable and predictive estimates on the efficiency and cost potential, as well as technologically feasible solutions. In this work, we elaborate on silicon bottom cell concepts based on the PERC, TOPCon, and SHJ technology combined with two different interconnection concepts. For each tandem device, the efficiency potential is investigated by means of an experimentally validated simulation model. Second, we evaluate the bottom cell concepts in terms of all‐in cell costs per piece. Bringing the efficiency potential and cost evaluation together allows us to assess the different tandem cell concepts in terms of all‐in module cost per watt peak. Our results show that perovskite–silicon tandem devices are promising candidates to significantly reduce the levelized cost of electricity and, in particular, that the "race" for the best silicon bottom cell is still open to all the investigated bottom cell technologies. [ABSTRACT FROM AUTHOR]

In this paper, an extensive investigation of low-frequency (1/f) noise and total ionizing dose–response of junctionless accumulation mode double-gate (JAM DG) MOSFET is presented. Current–voltage (Id–Vg) characteristics and low-frequency noise of JAM DG MOSFET are simulated at different ionized doses and compared to different gate oxide thickness and different channel doping concentrations. A significant amount of irradiation-induced threshold voltage shift and increase in low-frequency noise is observed for different gate oxide thickness and channel doping concentration. Moreover, the irradiation-induced border trap densities are also obtained at different doses. The gamma radiation model of Sentaurus TCAD is used to get the required results. [ABSTRACT FROM AUTHOR]

In this work, the impact of gate material work function on the sensitivity of dual-material, double-gate, junctionless MOSFET ( D M D G - J L - M O S F E T )-based biosensor has been studied. To enhance the sensitivity of the biosensor, optimization of gate work functions has been done through Sentaurus TCAD simulator. With the immobilization of biomolecules in the cavity at different value of work function of gate metal 1 (M1) and gate metal 2 (M2), i.e., WF1 and WF2, enhancement in sensing metrics (change in threshold voltage S V th and I ON / I OFF ratio) is observed. The enhancement in sensitivity is profound in source-side gate (M1) work function (WF1) optimization as compared to drain-side gate (M2) work function (WF2) optimization. Sensitivity of 90 mV is observed in source-side gate work function optimization which is ∼ 89% more than the sensitivity of 23 mV which is achieved in drain-side gate work function optimization for a fixed concentration and dielectric constant of biomolecules. It has also been noted that the proposed structure exhibits ∼ 90 % higher sensitivity than the single-material, dual-gate, junctionless MOSFET ( S M D G - J L - M O S F E T ) biosensor. Results showcase that the optimization of gate metal work functions enhances the sensitivity of the biosensor. [ABSTRACT FROM AUTHOR]

In this paper, a performance-improved AlGaN-/GaN-Based metal-insulator-semiconductor field effect transistor (MISFET) with double P-buried layers MISFET (DP-MISFET) is proposed. The proposed structure is simulated, and its characteristics are analyzed by the Sentaurus TCAD tool; the results show that with a gate-drain spacing of 6 μm, the optimized DP-MISFET can achieve high Baliga's figure of merit of 3.23 GW · cm-2 due to the modulation of the electric field distribution. Compared with the conventional MISFET (C-MISFET) with the breakdown voltage (BV) of 503.9 V and specific on-resistance (Ron,sp) of 0.63 mΩ · cm2, the proposed structure can achieve a better trade-off between the breakdown voltage and specific on-resistance achieving Ron,sp and BV of 0.63 mΩ · cm2 and 1427 V, respectively.

In this work, the authors study the performance of black phosphorus double gate MOSFET (BP‐DGMOSFET) within the ballistic limit. A hybrid simulation technique involving both atomistic and technology computer‐aided design (TCAD) tool has been used for the first time to simulate the device characteristics. First, the density functional theory has been used to simulate the electrical characteristics of single and fewlayer (five layers) phosphorene (including armchair and zigzag directions). The parameters such as bandgap and effective mass obtained using an atomistic simulator tool are exported into Sentaurus TCAD to simulate the BP‐DGMOSFET characteristics. They have used the kinetic velocity model and quantum model to account for the ballistic mobility and quantum effects in the device. The current drain characteristics are calibrated with non‐equilibrium Greens function (NEGF) simulation and radio frequency (RF) characteristics with compact model values and found that their results agree with them. Secondly, the other RF figure of merits, such as maximum frequency of oscillation, transconductance, output conductance and stability has also been simulated. It is found that their proposed method shows results comparable to NEGF with reduced computation time and complexity. [ABSTRACT FROM AUTHOR]

A novel double‐trench superjunction SiC metal–oxide–semiconductor field‐effect transistor (MOSFET) with an integrated Schottky contact at the drain side is proposed in this study. Results indicate an improvement of 58% in reverse recovery current Irrm/charge Qrr and 22% in the trench corner electric field Eox−m compared to the device without Schottky and without superjunction, respectively. This comparison became possible using mixed mode simulations in Sentaurus TCAD. While the improvement in electric field is due to incorporation of superjunction concept along the drift region, the improvement of reverse recovery is due to Schottky contact forming a barrier for the charge carriers. Using calibrated two‐dimensional numerical simulations, the authors were able to demonstrate the influence of Schottky contact on reverse recovery current of the device. The superiority of the proposed device is presented by plotting the switching energy loss with respect to external gate resistance and temperature through non‐isothermal simulations. [ABSTRACT FROM AUTHOR]

The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the effective drain current (Ieff) due to an enormous rise in short channel effects, such as subthreshold slope (SS) and drain-induced barrier lowering (DIBL). On the other hand, 5-nm diameter-based lateral nanowire shows an 80% rise in total current driving capability (Ieff). Therefore, to enable future devices, we explored electrostatics and effective drive current (Ieff) in FinFET, GAA-FET, and UFET architectures at a scaled dimension. The performances of both Si- and SiGe-based transistors are compared using an advanced device simulator, TCAD Sentaurus. [ABSTRACT FROM AUTHOR]

The optimum absorbing-layer thickness in the bottom In0.3Ga0.7As subcell of a triple-junction In0.3Ga0.7As/GaAs/In0.5Ga0.5P solar cell is sought for using the Sentaurus TCAD software package as a factor of the minority charge-carrier lifetime in this layer. The lifetime is set in the range from 17 ps to 53 ns. The calculation results show that the optimum thickness varies from 0.9 to 7.5 μm. In addition, the contribution of the bottom In0.3Ga0.7As subcell to the efficiency of this triple-junction solar cell is estimated at various lifetime values. Its value varies from 1 to 7%. [ABSTRACT FROM AUTHOR]

This work attempts to analyses the effect of oxide layer thickness on the performance of Underlap Double Gate (DG) AlInN/GaN Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) device. The device has a hetrostructure of lattice-matched wideband AlInN and narrowband GaN layers in the channel and Al2O3 in the oxide layer. The effect of Al2O3 thickness on device performance is analyzed using Sentaurus TCAD simulation software. The hydrodynamic model used in the simulation is calibrated with the previously published experimental result. A comprehensive, quantitative investigation of transfer characteristics, output characteristics, transconductance (gm), transconductance generation factor (TGF), threshold voltage (Vt), subthreshold slope (SS) and drain induced barrier lowering (DIBL) is done for varying Al2O3 thickness. As oxide thickness increases drain current ID, SS and DIBL increases. On the contrary, increase in oxide thickness results in decrease of gm, TGF and Vt decreases. These results demonstrate the feasibility of obtaining desired set of device properties by tuning the oxide thickness. [ABSTRACT FROM AUTHOR]

This article presents an electro-thermo-mechanical simulation of a SiC MOSFET transistor. The simulation was performed using Synopsis TCAD for electric modelling and ANSYS for thermo-mechanical modelling. A method upgrading stress estimation of a SiC MOSFET chip is suggested. It includes a bridge between Sentaurus TCAD and ANSYS mechanical, an aluminium's fusion model and a multiscale simulation. Finally, a difference between an isolated cell and a cell within a chip has been noticed. The results of the simulation provide valuable insights into the behaviour of SiC MOSFET transistors during short-circuit events. • Electro-thermo-mechanical simulation of a SiC MOSFET transistor under short-circuit • Multi-scale simulation by homogenisation • Sentaurus TCAD to ANSYS mechanical bridge [ABSTRACT FROM AUTHOR]

A novel method of stacking dielectric layers on top of Silicon carbide (SiC) is proposed to address the most common Silicon dioxide (SiO 2 )-SiC interface issues in SiC based metal oxide semiconductor (MOS) devices. Aluminum nitride (AlN) as an interfacial layer, instead of SiO 2 , between hafnium oxide (HfO 2 ) and SiC showed improved device characteristics. However, incorporating SiO 2 along with AlN as an interfacial layer is found to be the best way of stacking dielectric layers. This is concluded, based on the changes observed in the electrical characteristics of the device by intentionally varying lattice temperature (T), interface trap density (D it ) and junction field effect transistor (JFET) width. All the investigations are done in 4H-SiC half-cell planar n-channel MOS field effect transistor (MOSFET) using commercially available technology computer aided design (TCAD) software sentaurus device. Theoretical calculations show good agreement with the simulated results, and are compared with the published results. [ABSTRACT FROM AUTHOR]

Stress-engineered fin-shaped field effect transistors (FinFET) using germanium (Ge) is a promising performance booster to replace silicon (Si) due to its high holes mobility. This paper presents a three-dimensional simulation by the Sentaurus technology computer-aided design to study the effects of stressors--channel stress, stress-relaxed buffer (SRB), and source/drain (S/D) epitaxial stress--on different bases of FinFET, specifically silicon germanium (SiGe) and Ge-based, whereby the latter is achieved by manipulating the Ge mole fraction inside the three layers; their effects on the devices' figures-ofmerits were recorded. The simulation generates an advanced calibration process, by which the drift diffusion simulation was adopted for ballistic transport effects. The results show that current enhancement in p-type Fin- FET (p-FinFET) with 110% is almost twice that in n-type FinFET (n-FinFET) with 57%, with increasing strain inside the channel suggesting that the use of strain is more effective for holes. In SiGe-based n-FinFET, the use of a highstrained SRB layer can improve the drive current up to 112%, while the highstrain S/D epitaxial for Ge-based p-FinFET can enhance the on-state current to 262%. Further investigations show that the channel and S/D doping are affecting the performances of SiGe-based FinFET with similar importance. It is observed that doping concentrations play an important role in threshold voltage adjustment as well as in drive current and subthreshold leakage improvements. [ABSTRACT FROM AUTHOR]

In recent years, several experimental and simulation studies have been reported on the terahertz (THz) generation using a photoconductive antenna (PCA). The major problem with PCA is its low overall efficiency, which depends on several parameters related to a semiconductor material, an antenna geometry, and characteristics of the laser beam. To analyze the effect of different parameters on PCA efficiency, accurate circuit modeling, using physics undergoing in the device, is necessary. Although a few equivalent circuit models have been proposed in the literature, these models do not adequately capture the semiconductor physics in PCA. This paper presents an equivalent electrical circuit model of PCA incorporating basic semiconductor device physics. The proposed equivalent circuit model is validated using Sentaurus TCAD device level modeling tool as well as with the experimental results available in the literature. The results obtained from the proposed circuit model are in close agreement with the TCAD results as well as available experimental results. The proposed circuit model is expected to contribute towards future research efforts aimed at optimization of the performance of the PCA system. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id-Vg) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed.

This paper describes the TCAD-based design and verification of the different components of a 200 V GaN-on-SOI integrated circuits (ICs) platform developed on 200 mm substrates. This platform comprises of depletion-mode (d-mode) MIS-HEMTs, and Gated-Edge-Termination Schottky barrier diodes (GET-SBDs) monolithically integrated in an enhancement-mode (e-mode) HEMT technology baseline. A variety of low-voltage analog/logic devices and passive components further supports the GaN ICs platform. Device simulations have been verified using measured low voltage test structures. Verification of simulations with the measurements results in calibration of sheet resistance (R sh) in the gate and access region, threshold voltage (V th), drain current (I ds), ON-resistance (R ON), gate current (I g) for HEMT structures, and turn-on voltage (V T) and forward voltage drop (V F) for GET-SBD structure. • TCAD-based design and verification of different components on 200 V GaN IC platform • D-mode MIS-HEMT and GET-SBD are monolithically integrated with an e-mode technology • TCAD calibration flow for the Schottky diodes and d-mode HEMTs along with pGaN HEMTs • Optimize GaN-IC technology by calibrating the lateral co-integrated GaN power devices • Overlays of simulated and measured results for TCAD-based model verification [ABSTRACT FROM AUTHOR]

The influence of the doping concentration in the active layer and in the bulk substrate on the drain current of a silicon-on-insulator (SOI) field-effect Hall sensor (FEHS) using Sentaurus TCAD is studied. At the initial stage, the numerical model is corrected by comparing the transfer current-voltage characteristics of the calculation and the experimentally measured SOI FEHS sample. It is shown that, under low concentrations in the active layer, the drain current depends on the capacity of the front gate, while the doping concentration in the bulk substrate affects the drain current only when the device is operating in depletion mode. [ABSTRACT FROM AUTHOR]

This paper presents the MSM structure magnetic detector device that normally detects the electromagnetic wave. The device is special design for magnetic field detector and still detects the electromagnetic wave as normal function. The schottky diode with the split contacts structure allows us to reach this target. The device operates with the saturation current and the magnetic response is the current difference between two contacts which is injected from one metal and deflected in semiconductor toward to another metal. From the simulation result by Sentaurus TCAD, the relative sensitivity is 14.19 mT -1 at the current 0.3 μA. This device is the first MSM multi-sensor for magnetic and electromagnetic wave detector. [ABSTRACT FROM AUTHOR]

We couple numerical process and device simulations to provide a framework for understanding the combined effects of as-grown wafer impurity distribution, processing parameters, and solar cell architecture. For this study, we added the Impurity-to-Efficiency simulator to Synopsys’ Sentaurus Process software using the Alagator Scripting Language. Our results quantify how advanced processing can eliminate differences in efficiency due to different as-grown impurity concentrations and due to different area fractions of defective wafer regions. We identify combinations of as-grown impurity distributions and process parameters that produce solar cells limited by point defects and those that are limited by precipitated impurities. Gettering targeted at either point defect or precipitate reduction can then be designed and applied to increase cell efficiency. We also visualize the post-processing iron and total recombination distributions in 2D maps of the wafer cross-section. PV researchers and companies can input their initial iron distributions and processing parameters into our software and couple the resulting process simulation results with a solar cell device design of interest to conduct their own analyses. The Alagator scripts we developed are freely available online at http://pv.mit.edu/impurity-to-efficiency-i2e-simulator-for-sentaurus-tcad/. [ABSTRACT FROM AUTHOR]