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This brief presents a fully integrated nanoelectromechanical system (NEMS) resonator, operable at frequencies in the megahertz range, together with a compact built-in CMOS interfacing circuitry. The proposed low-power second-generation current conveyor circuit allows detailed read-out of the nanocantilever structure for either extraction of equivalent circuit models or comparative studies at different pressure and dc biasing conditions. In this sense, extensive experimental results are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing by nanostencil lithography. The proposed read-out scheme can be easily adapted to operate the nanocantilever in closed loop operation as a stand-alone NEMS oscillator. Index Terms--CMOS, current conveyor, low power, nanoelectromechanical systems (NEMS), read-out, resonator.

This paper presents both a complete set of very low-voltage basic building blocks and a compact design methodology for log filtering in standard or even digital CMOS technologies. The new proposals are based on an alternative translinear loop principle for the MOSFET operating in its subthreshold region. Three different sets of complete basic building blocks are proposed along with all required auxiliary circuitry and a specific matrix design procedure to obtain stable and compact filter implementations. Also, all-MOS filter implementations following these circuit techniques are studied. Simulated and experimental examples are given at 1-V supply voltage for 1.2- and 0.35-[micro]m CMOS technologies. The resulting circuit techniques are suitable to integrate very low-voltage low-power system-on-a-chip audio applications, such as hearing aids, in standard CMOS technologies. Index Terms--Analog, CMOS, companding, filtering, log domain, low voltage, subthreshold.

This paper presents a 1024-channel neural read-out integrated circuit (ROIC) for solution-gated GFET sensing probes in massive μ ECoG brain mapping. The proposed time-domain multiplexing of GFET-only arrays enables low-cost and scalable hybrid headstages. Low-power CMOS circuits are presented for the GFET analog frontend, including a CDS mechanism to improve preamplifier noise figures and 10-bit 10-kS/s A/D conversion. The 1024-channel ROIC has been fabricated in a standard 1.8-V 0.18-μm CMOS technology with 0.012 mm2 and 36 μW per channel. An automated methodology for the in-situ calibration of each GFET sensor is also proposed. Experimental ROIC tests are reported using a custom FPGA-based μ ECoG headstage with 16 × 32 and 32 × 32 GFET probes in saline solution and agar substrate. Compared to state-of-art neural ROICs, this work achieves the largest scalability in hybrid platforms and it allows the recording of infra-slow neural signals. [ABSTRACT FROM AUTHOR]

This paper presents a new low-power compact CMOS active pixel circuit specifically optimized for full-field digital mammography. The proposed digital pixel sensor (DPS) architecture includes self-bias capability at \pm10% accuracy, up to 15 nA of dark-current autocalibration, built-in test mechanisms, selectable e^-/h^+ collection, 10-b lossless charge-integration analog–to-digital conversion, more than 1 decade of individual gain tuning for fixed pattern noise cancellation, and a 50-Mb/s digital-only input/output interface. Experimental results for a 70-\mum pitch 8-\muW DPS cell example are reported in 0.18-\mum CMOS 1-polySi 6-metal technology. [ABSTRACT FROM PUBLISHER]

This paper presents a true very low-voltage low-power complete analog hearing-aid system-on-chip as a demonstrator of novel analog CMOS circuit techniques based on log companding processing and using MOS transistors operating in subthreshold. Low-voltage circuit implementations are given for all of the required functions including amplification and automatic gain control filtering, generation, and pulse-duration modulation. Based on these blocks, a single 1-V 300-μA application specific integrated circuit integrating a complete hearing aid in a standard 1.2-μm CMOS technology is presented along with exhaustive experimental data. To the authors' knowledge, the presented system is the only CMOS hearing aid with true internal operation at the battery supply voltage and with one of the lowest current consumptions reported in literature. The resulting low-voltage CMOS circuit techniques may also be applied to the design of A/D converters for digital hearing aids. [ABSTRACT FROM AUTHOR]

Presents the all-metal oxides semiconductors circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Basis of the optimization of supply scaling below the sum of threshold voltages; Key design equations for currents and voltage references; Suitability of PTAT circuits for very-low-voltage system-on-a-chip applications in digital CMOS technologies.