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Recently, there has been a lot of research in Quantum Cellular Automata (QCA) technology because it promises low power consumption, low complexity, low latency, and compact space. Simultaneously, approximate arithmetic, a new paradigm in computing, streamlines the computational process and emerges as a low-power, high-performance design approach for arithmetic circuits. Furthermore, the XOR gate has been widely used in digital design and is a basic building block that can be used in many upcoming technologies. The full adder (FA) circuit is a key component of QCA technology and is utilized in arithmetic logic operations including subtraction, multiplication, and division. A great deal of research has been done on the design of approximate FA, full subtractor (FS), full adder/subtractor (FA/S), and 4-bit ripple carry adder (RCA) based on XOR logic, establishing them as essential components in the creation of QCA-based arithmetic circuits. This study presents three new and effective QCA-based circuits, based on XOR logic: an approximate FA, an approximate FS, an approximate FA/S, and an approximate 4-bit ripple carry adder (RCA). Interestingly, some designs have inputs on one side and outputs on the other, making it easier to reach the components without being encircled by other cells and leading to a more effective circuit design. In particular, a delay of 0.5 clock phases, an area of 0.01 μm2, and implementation utilizing just 11 cells was accomplished in the approximate FA and subtractor designs. In a similar vein, the estimated FA/S designs showed 0.5 clock phase delay, 0.01 μm2 area, and 12 cells used for implementation. An approximate 4-bit RCA is proposed using 64 QCA cells. The effectiveness of these designs is evaluated through functional verification with the QCADesigner program. According to simulation results, these proposed solutions not only function well but significantly outperform previous ideas in terms of speed and space. The proposed FA, FS, and RCA designs surpassed the previous best designs by 21%, 21%, and 43%, respectively, in terms of cell count. [ABSTRACT FROM AUTHOR]

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Because of the high speed, low-power consumption, low latency and possible use at the atomic and molecular levels, Quantum-dot Cellular Automata (QCA) technology is one of the future nanoscale technologies that can replace the present transistor-based technology. For the purpose of creating QCA circuits, reversible logic can be regarded as an appropriate candidate. In this research, a new structure for multi-operative reversible designs is suggested. The Saeid Nima Gate (SNG), proposed in this research study, is a brand-new, incredibly effective, multi-operative, universal reversible gate implemented in QCA nanotechnology employing both majority and inverter gates. Reversible gates, also known as reversible logic gates, are gates that have n inputs and n outputs, which is an equal number of inputs and outputs. The amount of energy lost during computations will be reduced if the numbers of inputs and outputs are identical. The proposed gate is modified and reorganized to optimize further, employing exact QCA cell interaction. All fundamental logic gates are implemented using it to demonstrate the universality of the proposed SNG. Reversible logic has advanced, and as a result, our suggested solution has a lower quantum cost than previously reported systems. The suggested design is simulated using the QCADesigner-E tools. [ABSTRACT FROM AUTHOR]

The very-large-scale-integration industry has been highly trying to attain miniaturization. This function causes several challenges regarding size, switching speed, power, and fault-tolerant at the nanoscale. Quantum-dot cellular automata (QCA) can contain a remarkable reduction in scale, fast switching rate, ultra-low energy consumption, and high fault-tolerant. Thus, fault-tolerant logic has attained the attention of several investigators in the QCA science domain. On the other hand, a binary-to-gray converter converts the input data to the gray number to facilitate error correction in digital communication. So, in the present investigation, we have demonstrated a structure of fault-tolerant binary-to-gray converter in QCA employing the majority gate, inverter gate, and cell redundancy on the wire. With the utilization of the QCADesigner 2.0.3 simulator, we have simulated and tested proposed circuits. In this paper, four factors, namely single-cell missing, displacement, misalignment, and extra single-cell, have been inspected by simulation software. The proposed fault-tolerant two-bit, three-bit, and four-bit binary-to-gray converter could attain 100% fault tolerance while a single missing defect existed in the layout. [ABSTRACT FROM AUTHOR]

Recently, quantum dot‐cellular automata (QCA) has fascinated much attention because of its potential less area consumption, low power usage, less intricacy, and low delay. The full‐adder circuit is used in this technology for several procedures, like multiplication, subtraction, and division in the arithmetic logic unit. For this reason, the full‐adder is generally investigated as a central unit in the development of QCA technology. The present investigation demonstrates a new efficient QCA‐based full‐adder layout utilizing the TIEO gate and new 3‐input majority gate. In this design, the inputs get inside one side, and the outputs are derived from another circuit side. Other cells do not embrace the output and input signals, and they may simply be available, helping produce a more impressive circuit layout. Concretely speaking, in this design, the 0.02 μm2 region and the latency of the 0.5 clock cycle have been implemented using only 18 cells. Utilizing the QCADesigner tool, the suggested design in the current investigation has been functionally approved. The simulation outcomes show that this layout conducts properly and works faster than the oldest designs. [ABSTRACT FROM AUTHOR]

Quantum‐dot cellular automata (QCA) is one of the best methods to implement digital circuits at nanoscale. It has excellent potential with high density, fast switching speed, and low energy consumption. Researchers have emphasized reducing the number of gates, the delay, and the cell count in QCA technology. In addition, a ripple carry adder (RCA) is a circuit in which each full adder's carry‐out is the connection for the next full adder's carry‐in. These types of adders are quite simple and easily expandable to any desired size. However, they are relatively slow because carries may broadcast across the entire adder. Therefore, an RCA design on a nanoscale QCA is proposed to diminish the cell number, improve complexity, and decrease latency. The QCADesigner simulation tool is used to verify the correctness of the suggested circuit. The comparison results for the design indicate an approximately 49.14% improvement in cell number and 14.29% advantage in area for the state‐of‐the‐art 4‐bit RCA designs with QCA technology. In addition, the obtained results specify the effectiveness of the offered design. [ABSTRACT FROM AUTHOR]