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Chemical mechanical polishing (CMP) is a committed step in the manufacturing of integrated circuits, especially in the fabrication process of shallow trench isolation (STI) structures. Ceria (CeO2) slurry is widely used in the STI CMP process, while it is vulnerable to causing surface defects owing to particle agglomeration, such as scratches and abrasive residues. Furthermore, CeO2 slurry faces the challenge of low polishing removal selectivity between silicon dioxide (SiO2) and silicon nitride (Si3N4) surfaces. In this study, we investigated the effects of various non-ionic surfactants and different pH levels in CeO2-based slurries on material removal rates, removal selectivity, and surface qualities of polished wafers. Two of the studied non-ionic surfactants that make CeO2 slurries disperse better were selected through sedimentation experiments, which were polyethylpyrrolidone (PVP-K30) and polyethylene glycol, respectively. Subsequently, polishing experiments and atomic force microscopy characterization tests were conducted to illustrate the effects of the selected surfactants at different pH conditions. To further explore the underlying mechanism, the reaction of surfactants on SiO2 and Si3N4 wafers was explained using surface adsorption tests, thermogravimetry experiments, zeta potential measurements, and chemical valence bond structure analysis. As a result, it can be concluded that the performance of ceria slurries used in STI CMP process can be improved by the addition of non-ionic surfactant PVP-K30. [ABSTRACT FROM AUTHOR]

AbstractAs the development of technology nodes proceeds to 7 nm node, chemical mechanical polishing (CMP) slurries for shallow trench isolation (STI) cannot fully meet the technical requirements. Higher goals are put forward for the polished surface qualities and the removal selectivity control. The polishing liquid exhibits issues such as easy agglomeration, removal rate of Si3N4 exceeding 50 Å/min, removal selectivity ratio of SiO2/Si3N4 below 20, increased surface scratches and roughness of SiO2 and Si3N4 after polishing exceeding 1 nm. Here, attention is given to studying the STI CMP process by introducing various ionic surfactants in ceria slurries, aiming to control removal rates, selectivity, as well as surface qualities. The findings of ball milling and settling tests were used as a starting point for choosing the effective surfactants, searching the minimal delamination phenomenon. Then the impact of surfactants on removal rates, selectivity and surface characteristics were next investigated in polishing trials at various pH levels. Depth of scratches on polished wafers and corresponding surface roughness, as well as morphology of ceria abrasive particles were characterized. Action mechanisms of selected ionic surfactants in ceria slurries have been revealed by solid-liquid interface adsorption characterization, thermogravimetric analysis and zeta potential tests. Through research finding the addition of piperazine and 2-methylpiperazine surfactant can reduce the number and depth of scratches on the surfaces of SiO2 and Si3N4 after polishing, and it exhibits better dispersibility in alkaline environment compared to acidic environment.

As the development of technology nodes proceeds to 7 nm node, chemical mechanical polishing (CMP) slurries for shallow trench isolation (STI) cannot fully meet the technical requirements. Higher goals are put forward for the polished surface qualities and the removal selectivity control. The polishing liquid exhibits issues such as easy agglomeration, removal rate of Si3N4 exceeding 50 Å/min, removal selectivity ratio of SiO2/Si3N4 below 20, increased surface scratches and roughness of SiO2 and Si3N4 after polishing exceeding 1 nm. Here, attention is given to studying the STI CMP process by introducing various ionic surfactants in ceria slurries, aiming to control removal rates, selectivity, as well as surface qualities. The findings of ball milling and settling tests were used as a starting point for choosing the effective surfactants, searching the minimal delamination phenomenon. Then the impact of surfactants on removal rates, selectivity and surface characteristics were next investigated in polishing trials at various pH levels. Depth of scratches on polished wafers and corresponding surface roughness, as well as morphology of ceria abrasive particles were characterized. Action mechanisms of selected ionic surfactants in ceria slurries have been revealed by solid-liquid interface adsorption characterization, thermogravimetric analysis and zeta potential tests. Through research finding the addition of piperazine and 2-methylpiperazine surfactant can reduce the number and depth of scratches on the surfaces of SiO2 and Si3N4 after polishing, and it exhibits better dispersibility in alkaline environment compared to acidic environment. [ABSTRACT FROM AUTHOR]

This study presents an accurate model for non-monotonic layout-dependent effects (LDEs) measured using 10nm-class dynamic random access memory technology. To collect the LDE measurement data, a test module with an individually addressable array of 240 transistors has been developed. The proposed test module occupies a small area of 0.1 square millimeters with a density 15 times higher than that of typical scribe-line circuits. The proposed model employs a novel empirical function to precisely describe the non-monotonic dependence on each pair of geometrical parameters, such as the diffusion lengths, lateral/vertical spacings to the adjacent shallow trench isolations, and gate-to-contact distances. Additionally, this model can be easily realized as a sub-circuit model in standard circuit simulators, requiring only two additional tuning parameters for the core transistor. The fitted model demonstrates excellent agreement with the measured values obtained from test modules (802 transistors in total), achieving mean absolute errors of 0.7% for the drain current in the saturation region and 4.7 mV for the threshold voltage.

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This study concerns the development of a gap-fill process technology for isolating trench patterns. There are various gap-filling techniques in the case of trench patterns; nevertheless, a processing technology adopting the DED (deposition/etch/deposition) method was developed in this study. After the etch step, an Ar/O2 (1:2) plasma treatment technology reduced the residual amount of F in the films to 0.05%. By improving the etch uniformity, the deposition uniformity after the DED process on a 12-inch flat wafer was secured within <1%, and a high-quality SiO2 thin film with a dielectric constant of 3.97 and a breakdown field of 11.41 MV/cm was fabricated. The DED method can be used for gap-filling even in patterns with a high aspect ratio by changing process parameters, such as RF power and division of etch steps, according to the shape, depth, and CD size of the pattern. This study confirmed that a void-free gap-fill process can be developed in a trench pattern with a maximum aspect ratio of 40:1. [ABSTRACT FROM AUTHOR]

Copyright of Electroplating & Finishing is the property of Electroplating & Finishing Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This article investigates the device variability induced by the total ionizing dose (TID) effects in a commercial 16-nm bulk nFinFETs, using specially designed test structures and measurement procedures aimed at maximizing the matching between devices. DC static characteristic measurements show that below 100 Mrad(SiO2) the device variability is slightly affected by the total accumulated dose. However, when the total dose reaches 100 Mrad(SiO2), the device variability increases significantly showing a correlation with pre-irradiation electrical responses of the devices. Transistors characterized by higher drain current exhibit the worst TID degradation. This phenomenon is likely due to the impact of random dopant fluctuations on the TID effects and/or to variations in the hydrogen concentration responsible for the TID-induced interface traps. [ABSTRACT FROM AUTHOR]

The features of collecting minority charge carriers formed on the tracks of single particles in a layer of silicon at a depth of 200 to 250 nm under shallow trench isolation (STI) in a CMOS two-input NAND gate and an inverter as part of the majority gate are simulated using 3D TCAD utilities. Charge collection by groups of two NMOS and two PMOS transistors, as well as one PMOS transistor, when collecting charge from tracks with input track points into the silicon's active areas of the transistors and surrounding the STI at distances of 40 to 700 nm from the edge of the transistor groups, is investigated. The charges transferred by current pulses from these distances ranges from 50 to 4.5 fC at LET = 60 MeV cm2/mg and from 80 to 11 fC at LET = 90 MeV cm2/mg. Increasing the distance of the track's entry point into the trench isolation by 200 nm from the area of the group of transistors that collect charge from the track reduces the amplitude value of the current pulse that transfers the charge from the track by factors of 1.8 to 2.0 times and also halves the value of the collected charge. At LET = 90 MeV cm2/mg, the amplitude values of voltage pulses at the node that outputs the charge with two NMOS or two PMOS transistors of a two-input NAND gate in the track entry points ranging from 40 to 200 nm can decrease by factors of 1.5 to 2.0 with an increase in the distance of the track entry point by 100 nm from the edge of the transistor area. Error pulses at the output of the majority gate with an amplitude of 0.7 to 1 V are formed at the track entry points directly in the active areas of the NMOS and PMOS transistors and in tracks with entry points into the STI layer at a distance of 40 to 100 nm from the edge of the active areas, mainly during charge collection by the NMOS transistors. [ABSTRACT FROM AUTHOR]

High-density memories and high-speed CPUs are usually realized by reduction of the size of semiconductor cells in Large Scale Integrations (LSIs). Representative length scale of Ultra Large Scale Integration (ULSI) cells is going to be in nano-meter order. Dislocation accumulation during the production process in the electron channel of semiconductor device is one of the most serious problems. Dislocation accumulation has an enormous effect on the electronic state of the device. Therefore, the evaluation and suppression of dislocation accumulation are crucially important for the design and development of semiconductor device structure. In this study, we numerically analyze the suppression of dislocation accumulation in the shallow trench isolation type ULSI cells. Accumulation of dislocations is analyzed by employing a technique of crystal plasticity analysis and we evaluate the dislocation density distribution and total length of dislocations in the silicon substrate. Possibilities for the suppression of dislocation accumulation are discussed.

The adoption of ultra-fine nanoparticles as an abrasive has garnered notable attention in shallow trench isolation (STI) chemical mechanical planarization (CMP) due to its potential in scratch reduction. However, the poor removal rate, attributed to the physicochemical interaction between abrasive and conventional organic passivation agent, limits the introduction of ultra-fine nanoparticles. Here, a nonionic polymer polyvinyl alcohol (PVA), without particle interaction, is proposed as a novel passivation agent to restrict the hydrolysis reaction of Si 3 N 4 film in the advanced STI CMP process. The selective adsorption of PVA onto the Si 3 N 4 film lowers its removal rate by suppressing the hydrolysis reaction via hydrogen bonding while the removal rate of SiO 2 film remains constant. Moreover, the uniformity of SiO 2 removal is improved due to the enhanced fluidity of slurry, resulting from increased wettability between pad and slurry. As a result, the removal selectivity between both films has been improved to 113.4:1 and the in-wafer-uniformity (IWU) of SiO 2 film is supplemented by 96.8 % simultaneously. [Display omitted] • Polyvinyl alcohol (PVA), a nonionic polymer, was proposed as a passivation agent for Si 3 N 4 film during advanced STI CMP. • PVA adsorption onto the Si 3 N 4 via hydrogen bonding suppresses hydrolysis of Si 3 N 4 , resulting in drastic removal reduction. • The uniformity of SiO 2 removal was improved due to the increase in wettability. • The removal selectivity between SiO 2 and Si 3 N 4 films has been improved to 113.4:1. [ABSTRACT FROM AUTHOR]

Abstract The n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) produced in the widely used CMOS bulk process takes radiation damage by the total ionizing dose (TID) effects in radiation environments, so the radiation-tolerant properties of semiconductor integrated-circuits (ICs) used in high-radiation environments is a critical issue. The formation method of the isolation oxide module (IOM), which induces the radiation-induced leakage currents, differs depending on the chip density of the CMOS bulk process. In this paper, we designed and fabricated I-gate n-MOSFETs for bulk process and analyzed the radiation-tolerant characteristics according to IOM. The I-gate n-MOSFET chips are fabricated using the shallow trench isolation (STI) 0.18um and local oxidation of silicon (LOCOS) 0.35um processes of the CMOS bulk process. Tests and evaluation of the TID effects on the chips are carried out by irradiating a total cumulative dose up to 2 Mrad(Si). As the results, in the standard n-MOSFET, the leakage currents of the LOCOS and STI processes are 27.7uA and 16.4uA, and in I-gate n-MOSEFT, are 1.1uA and 0.7uA. The leakage currents of standard n-MOSFET increased by about 25 times before and after irradiation, but the electric characteristics of I-gate n-MOSFET is maintained regardless of the process. Therefore, the process versatility of the I-gate n-MOSFET with the radiation-tolerant performance has been verified. Graphical abstract Unlabelled Image Highlights • Radiation-induced TID effects that forms the leakage current of the electronic device. • Implementation of n-MOSFET with I-gate structure to block leakage current. • Verification of radiation-tolerance characteristics in LOCOS and STI process through TID effect test. • Process versatility for designing radiation integrated circuits. [ABSTRACT FROM AUTHOR]

Two types of transient leakages in gate oxide due to charge traps and phosphorus contaminants induced during gate oxidation processing have been extensively examined. The reliability of gate oxide grown from a corroded silicon surface was degraded by the existence of charge traps locally on the pitted spots, resulting in irregularly transient leakages and early breakdowns. The regular transiency of leakages specifically within p -type gate oxide has been elucidated for the first time in connection with the excessive phosphorus contaminants as a constant source of defects at gate oxidation. By avoiding silicon surface corrosion or significant build-up of phosphorus contaminants, the gate oxide defects causing transient leakages have been eliminated and process robustness has been improved. [ABSTRACT FROM AUTHOR]

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes. [ABSTRACT FROM AUTHOR]

Finite Elements Method simulation of Total Ionizing Dose effects on 22 nm bulk Fin Field Effect Transistor (FinFET) devices using the commercial software Synopsys Sentaurus TCAD is presented. The simulation parameters are extracted by calibrating the charge trapping model to experimental results on 400 nm SiO 2 capacitors irradiated under zero bias. The FinFET device characteristics are calibrated to the Intel 22 nm bulk technology. Irradiation simulations of the transistor performed with all terminals unbiased reveal increased hardness up to a total dose of 1 MRad(SiO 2 ). [ABSTRACT FROM AUTHOR]

Ultra Large Scale Integration (ULSI) are usually realized by a reduction of the size and high integration of semiconductor devices. In recent years, representative length scale of ULSI cells is going to be at a nanometre order. Several atomic level problems like a generation of lattice defects are taking place in the fabrication processes when the semiconductor device size becomes small. Dislocations often appear near hetero-interfaces and accumulate in the electron channel of semiconductor device is one of the most serious problems. Therefore, the evaluation and control of dislocation accumulation are crucially important for the design and development of semiconductor device structure. Generation and accumulation of dislocations are known to take place during the formation of thermal oxide film, and the cooling processes of semiconductor device fabrication. In this study, we simulate the dislocation accumulation during the formation of thermal oxide film of device fabrication process. Accumulation of dislocation is analysed by employing a technique of crystal plasticity analysis and evaluate the stress distribution, dislocation density distribution in the silicon substrate and structure of dislocation accumulation. Relations between the geometry of the shallow trench isolation type ULSI cells and dislocation accumulation are discussed.

Given the reduction in size of hole-containing metal-oxide-semiconductor field-effect transistors (pMOSFETs) to break Moore's law, extensive researches have been conducted to improve the performance of nano-scaled devices with the use of strained engineering. The layout patterns of devices combined with the introductions of manufacturing processes would cause recessed surfaces of shallow trench isolation (STI) and change the stress-induced mobility of the whole transistors. To address this issue, a process-oriented stress simulation with a 20 nm nano-scaled short channel device and a 100 nm gate width is presented to extract channel stress components and calculate mobility gain, subsequently. Moreover, the layout effect of dummy active of diffusion is also considered. The proposed pMOSFET is composed of STI, a source/drain lattice mismatched silicon-germanium alloy, and a compressed contact etch stop liner (CESL) stressor. The recessed height of STI is reduced from 0 nm to 15 nm in the planarization process. The results show the recessed height effects of STI on the stresses and mobility variation of device channel is not obvious. By contrast, CESL with intrinsic stress plays an important role to modulate device mobility. [ABSTRACT FROM AUTHOR]