15 results on '"Sharan, Neha"'
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2. Design and Performance Comparison of CNTFET-Based Binary and Ternary Logic Inverter and Decoder With 32 nm CMOS Technology
3. Continuity equation based nonquasi-static charge model for independent double gate MOSFET
4. Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies
5. Ge Devices: A Potential Candidate for Sub-5-nm Nodes?
6. Cost Effective FinFET Platform for Stand Alone DRAM 1Y and Beyond Memory Periphery
7. Characterization of 6T CMOS SRAM in 90nm technology for various leakage reduction techniques
8. Compact noise modelling for common double‐gate metal–oxide–semiconductor field‐effect transistor adapted to gate‐oxide‐thickness asymmetry
9. indDG: A new compact model for common double gate MOSFET adapted to gate oxide thickness asymmetry
10. Reliable techniques of leakage current reduction for SRAM-6T Cell: A review.
11. A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry
12. Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry
13. Continuity equation based nonquasi-static charge model for independent double gate MOSFET
14. Nonquasi-Static Charge Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry
15. Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETs
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