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A new approach for designing a quaternary arithmetic logic unit (ALU) based on carbon nanotube field-effect transistors (CNTFETs) is presented in this paper. The proposed design performs basic arithmetic and logic functions and is extendable to perform additional functions (both arithmetic and logic functions). Efficient circuit-level optimisation techniques such as data gating are used to reduce the power consumption and enhance the performance of the proposed design. In addition, the unique properties of CNTFETs such as adjusting the threshold voltages of CNTFETs by tuning the CNTs diameters are utilised for designing a quaternary ALU. The proposed design is simulated and examined in different conditions and in the presence of major process variations using the Synopsys HSPICE simulator with Stanford 32nm CNTFET technology. [ABSTRACT FROM AUTHOR]

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET technology. The proposed methods are simulated at different conditions such as different supply voltages, different temperature, and operational frequencies. Simulation results show that the proposed designs are faster than the state of the art CNFET-based ternary full adders. [ABSTRACT FROM AUTHOR]