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The extensive amount of data and contents generated today will require a paradigm shift in processing and management techniques for these data. One of the important data processing operations is the data sorting. Using multiple passes in external merge sort has a great influence on speeding up the sorting of extremely large data files. Since in large files, the swapping time is dominant in many applications, algorithms that minimize the swapping operations are normally superior to those which only focus on CPU time optimizations. In sorting extremely large files, external algorithms, such as the merge sort, are normally used. It is shown that using multiple passes over the data set, as proposed in our algorithm, has resulted in a great improvement in the number of swaps, thus, reducing the overall sorting time. Moreover, the proposed technique is suitable to be used with the emerging parallelization techniques such as GPUs. The reported results show the superiority of the proposed technique for "CPU only" and hybrid CPU–GPU implementations. [ABSTRACT FROM AUTHOR]

In this paper, two essential components of the Flash ADC are designed and integrated within a new Flash ADC architecture. The power consumption is reduced by realizing a switched-capacitor positive feedback (SCPF) comparators structure as a replacement for conventional comparators structure. The SCPF comparator is tailored to a single-ended input/single-ended output configuration that operates in two steps: offset-cancelation function followed by comparison decision. Furthermore, the encoding stage is implemented using N parallel independent components of one single AND gate each, where N is the number of quantized regions. This structure provides fast encoding with minimal encoding activities. The design architecture exploits two stages, which are separated by latches. The first stage allocates the analog input to a quantized region, while the second stage converts the level of the quantized region into its corresponding binary code. This separation is considered the key success for incorporating the SCPF comparators structure into our Flash ADC architecture. HSPICE simulations of the proposed design use 35 nm Synopsys FinFet technology and 1-V power supply. The simulation results show that our 5-bit Flash ADC can function at a sampling frequency of up to 1 GHz, with an input signal of 500 MHz at Nyquist rate, where the amplitude input signal is ranging from 0.2 to 0.8 V with an overall maximum power consumption of 3 mW. [ABSTRACT FROM AUTHOR]

The cache memory has a direct effect on the performance of a computer system. Instructions and data are fetched from a fast cache instead of a slow memory to save hundreds of cycles. Reducing the cache miss ratio will definitely improve the execution time of an application. In this work, we propose cache memory designs that reduce the number of conflict misses significantly. The proposed designs reduce the conflict misses in the last level multi-way set associative cache. Each set is divided into a group of subsets: the first is referred to as the exclusive subset, and the rest are the shared subsets. The exclusive is configured as a traditional cache where each block is mapped to the set whose index matches the block index. In addition to their standard cache indexing role, the shared subsets are configured to host blocks with different indices. A memory block can be mapped to one subset from the exclusive type or one of multiple subsets from the shared type. Since the proposed technique is based on combining multiple sets of the shared part to form a larger set, that is shared between memory blocks with different indices, we have chosen the name “set folding.” The decision as to where to map a memory block depends on the number of misses encountered at each of the potential target sets. To evaluate the proposed design based on the overall hit rate, twenty-three benchmarks from SPEC CPU 2006 were simulated using the SuperESCalar simulator. The proposed designs require a few extra storage bits which adds a small overhead on the hardware complexity in comparison with the conventional cache. However, the proposed designs achieve lower miss rates for most of the benchmarks. [ABSTRACT FROM AUTHOR]

Abstract: A technique for scheduling and processor allocation leading to the synthesis of integrated heterogeneous pipelined processing elements, implementing digital signal processing applications, is proposed. The proposed technique achieves efficient hardware implementations at the logic-level by minimizing the number of processing units used, without compromising the rate and delay optimality criteria. The proposed algorithm is found to outperform algorithms resulting in homogeneous implementations, as it gives schedules with lower iteration periods, requires less hardware resources, and has lower time complexity at design time. In comparison with the already existing heterogeneous algorithms, the proposed algorithm produces schedules of lower time complexity and lower iteration period for some applications. The optimal performance of the proposed algorithm has been verified on several benchmarks. [Copyright &y& Elsevier]

Over the last few decades, many improved Evolutionary Algorithms (EAs) have been proposed to tackle different types of optimization problems. Genetic Algorithm (GA) among other canonical algorithms have not shown consistent performance over a range of different optimization problems with complex characteristics. In this paper, an improved class of real-coded Genetic Algorithm is introduced to solve complex optimization problems. The first algorithm, Genetic Algorithm embedded with a new Differential Evolution crossover, GA–DEx, proposes a new variant of Differential Evolution mutation which is used as a new multi-parent crossover in Genetic Algorithms. The main purpose of this algorithm is to enhance the search ability of the GA algorithm by combining a new Differential Evolution crossover with a GA algorithm to avoid premature convergence and stagnation scenarios by exploring more solutions in the problem search space. The second amalgam algorithm, GA–DEx SPS , uses an effective and efficient successful parent selection strategy to provide a successful alternative for the selection of parents during the Differential Evolution crossover process. This strategy improves the performance of first introduced algorithm by selecting more promising parents to guide the evolutionary search. The third algorithm, GA– a DEx SPS , introduces an aging mechanism and a success-history-based adaptive Genetic Algorithm. This algorithm adapts the alpha parameter used by Differential Evolution crossover in a history-based adaptive manner. This adaptation helps the search to discover more promising regions and to prevent stagnation and premature convergence scenarios. To verify the performance of our class, a challenging test suite of 30 benchmark functions from the IEEE CEC2014 real parameter single objective competition is used. The results affirm the effectiveness and robustness of the proposed algorithms compared to other state-of-the-art well-known crossovers and recent Genetic Algorithms variants. [ABSTRACT FROM AUTHOR]