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A digitally controlled oscillator (DCO) is presented that utilizes the non-linearity of a resistor-triode combination in conjunction with a weak latch to mitigate the supply sensitivity of inverter-based delay cells and remain supply noise insensitive over a wide range of supply variation. A proof-of-concept prototype for the DCO in 65 nm-CMOS process occupies $90\times 210\,\,\mu \text{m}\,\,^{\mathrm{ 2}}$ area and consumes 2.25 mW operating over a range of 0.9–1.4 GHz output frequency. At 850 Mv-supply voltage, the frequency pushing of DCO is zero at the optimal point and remains less than 10% over a large excursion of 50 mVpp. When embedded into an all-digital phase locked loop, closed-loop measurements demonstrate that supply noise with 50 mVppmagnitude does not impact the loop dynamics. [ABSTRACT FROM AUTHOR]

A 1.5–1.6 GHz dual-loop phase-locked loop in 0.18-\mu\ m CMOS locks in 40 \mu\ s and draws only 26 mA from 1.8 V . The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state operation. The integrated RMS phase error is 1.1^\circ and the phase noise spectral density is - \ 116.8~\ dBc/\ Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are - \ 83~\ dBc and - \ 105~\ dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively. [ABSTRACT FROM PUBLISHER]

A general model for injection-locked LC oscillators (LC-ILOs) is presented that is valid for any tank quality factor and injection strength. Important properties of an ILO such as lock-range, phase shift, bandwidth and response to input jitter are described. An LC-ILO together with a half-rate data sampler is implemented as a forwarded-clock I/O receiver in 45-nm CMOS. A strongly-injected low-Q LC oscillator enables clock deskew across 1UI and rejects high-frequency clock jitter. The complete 27 Gb/s ILO-based data receiver has an overall power efficiency of 1.6 mW/Gb/s. [ABSTRACT FROM AUTHOR]

Time-domain responses of wideband CMOS amplifiers using several inductive peaking techniques are presented. Transient performance considerations are described, including the effects of transistor parasitics on settling and edge rates. A combination of time- and frequency-domain performance is derived for a given bandwidth extension technique, and tradeoffs are discussed. Measured results for several high-speed high-gain single-stage amplifiers are presented in 0.18-µm CMOS, and a design strategy for multistage amplifiers is introduced. Finally, design and simulation results are presented for a multistage amplifier in 0.18-µm CMOS that attains a bandwidth of 22.7 GHz with 14.7-dB voltage gain, operates at 40 Gb/s, and consumes 93.6 mW. [ABSTRACT FROM AUTHOR]

This paper investigates the suitability of full duplex simultaneous bidirectional (FD-SBD) signaling as a method to theoretically double the aggregate data transfer per pin for ultra-short-reach links. Advantages as well as challenges associated with differential FD-SBD links are described, and comparisons are made with single-ended and multilevel signaling schemes. FD-SBD links require a hybrid to recover the weak received signal from the large self-interfering transmitted signal. After providing a summary of prior-art high-speed hybrids, which often utilize replica drivers and current-mode signaling, two voltage-mode hybrids are presented and compared to enable low-power FD-SBD links at high data rates without using any replica drivers. This includes an R- $G_{m}$ driver, as well as a resistor-bridge driver derived from a Wheatstone-bridge. It is shown that maintaining a uniform termination impedance is important to support FD-SBD signaling on low insertion-loss links. Accordingly, a resistor-bridge hybrid utilizing an averaging resistor embedded in the output transimpedance amplifier based voltage-mode driver is implemented. A prototype implemented in a 65 nm CMOS process is measured within a transceiver front-end at an aggregate data rate of 15 Gb/s over a short differential channel with 2.5 dB insertion loss at 3.75 GHz on a 4-layer FR4 PCB. The energy/bit for the transceiver front-end is 1.35 pJ/b at an aggregate data rate of 15 Gb/s. [ABSTRACT FROM AUTHOR]

Improving power-conversion efficiency (PCE) of VCSEL drivers is paramount to improve the overall energy efficiency of the entire optical link for high-performance computing and datacenters. VCSEL diodes are normally driven single-ended with pseudo-differential current-mode drivers to maintain signal integrity. However, such conventional drivers consume significant power and are often unable to compensate for supply switching noise due to package parasitics at high data-rates. We propose a differential push-pull voltage-mode VCSEL driver to mitigate bondwire parasitics, reduce power consumption, and leverage CMOS process scaling to its maximum advantage. A proof-of-concept prototype in 65-nm CMOS process achieves the highest ever-reported PCE of 18.7 % for VCSEL drivers when normalized to VCSEL slope efficiency. It uses an asymmetric 3-tap rise and fall-based pre-emphasis to achieve a total energy/bit of 1.52 pJ/b at 16 Gb/s with an average optical power output of 1.34 dBm, OMA of 2.1 dBm, and extinction ratio of 5.92 dB. [ABSTRACT FROM AUTHOR]

Varactors in RF CMOS processes often have significantly lower Q- factor ($Q_{VAR}$) than inductors and transformers at mm-wave frequencies. Direct connection of varactors to the outputs of an LC oscillator lowers overall tank Q, $Q_{T} < Q_{VAR}$ , and at the same time, increases the ratio of parasitic capacitance to total tank capacitance which limits frequency tuning range (FTR). Instead, magnetically coupling a varactor to the oscillator core using an asymmetric transformer, where the core is connected to the primary and varactor to the secondary, limits the drop in $Q_{T}$. The ratio of parasitic capacitance to total tank capacitance is also reduced. The varactor can also be operated in accumulation-mode, with a larger $Q_{VAR}$. Thus, both FTR and phase noise (PN), in comparison to traditional tanks in LC VCOs, are improved simultaneously. In this paper, two VCO prototypes are implemented in 65-nm CMOS. A 60 GHz self-mixing VCO with a VCO core operating at 20 GHz shows an FTR of 18.5%, a PN of −92.5 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −187.1 dBc/Hz. A 25 GHz VCO shows an FTR of 29.9%, a PN of −107.9 dBc/Hz at 1 MHz offset, and an FoM $_{T}$ of −194.2 dBc/Hz. [ABSTRACT FROM AUTHOR]

This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art. [ABSTRACT FROM AUTHOR]

Avalanche photodetectors (APDs) improve the sensitivity of optoelectronic (O/E) receivers (RXs) due to their high multiplication gain and responsivity. When implemented monolithically with a CMOS transimpedance amplifier (TIA) on the same chip, they provide further advantages, such as low cost and reduced parasitics. However, APDs require high bias voltages, are sensitive to variations in operating conditions, and have a limited gain-bandwidth product. This paper presents an 850 nm APD implemented in a standard 0.13- $\mu \text{m}$ CMOS process with a responsivity of 3.92 A/W and a large-signal −3 dB bandwidth of 3.5 GHz. Advantages of on-chip integration with a TIA are described and a noise-canceling active balun following the single-ended TIA is presented. The O/E-RXs front-end achieves a measured sensitivity of −18.8 dBm, the best-reported among 10 Gb/s linear CMOS TIAs operating at 850 nm. The energy/bit is 0.57 pJ/b. An on-chip voltage booster is described and implemented to generate a large APD bias using nominal CMOS voltage supplies. A modified hill-climbing algorithm is also presented that can enable bias stabilization for the voltage booster and the optoelectronic front-end for a complete all-bulk-CMOS implementation. [ABSTRACT FROM AUTHOR]

A passive, time-domain equalizer is presented that achieves a broadband self-interference cancellation (SIC) over 80 MHz of RF bandwidth for simultaneous full-duplex radios. A baseband Hilbert transform technique reduces the number of equalizer taps needed for SIC, and with frequency translations, results in an equivalent RF-domain equalization. A proof-of-concept prototype in 0.13- $\mu \text{m}$ CMOS process attains a measured 23 dB of SIC over an 80 MHz signal bandwidth at 900 MHz, and consumes 13 mW of clocking power independent of SIC equalizer settings. Its impact on the receiver noise figure is 1.4 dB. The equalizer and the receiver together consume 64.4 mW from a 1.2 V supply in an active area of 0.72 mm2. [ABSTRACT FROM AUTHOR]

Despite their inherent stability, area-efficient loop filters, and insensitivity to phase-frequency detector nonlinearity and dead-zone, type-I phase-locked loops (PLLs) are used infrequently because of two major limitations—limited lock-range and large reference spurs. This paper introduces a type-I PLL that takes advantage of the inherent benefits of the architecture, while tackling its limitations by means of gain boosting in the forward path for lock-range improvement and synchronous peak tracking of the voltage-controlled oscillator control voltage for reference spur reduction. Sampling in the loop filter changes the loop dynamics, and methods to accurately predict the closed-loop response, starting from state-space equations, are provided. A digital-friendly, voltage-mode topology is proposed that does not need charge pumps or opamps. A prototype 2.2–2.8-GHz PLL occupies a core area of 0.12 mm2 in 0.13- $\mu \text{m}$ CMOS and achieves −103.4 dBc/Hz in-band phase noise, −65-dBc reference spur, and 2.5- $\mu \text{s}$ worst-case lock-time while consuming 6.8 mW from a 1.2-V supply. [ABSTRACT FROM AUTHOR]