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31 results on '"Shen, Tien-Lin"'

14. Integration of Nanoscale and Macroscale Graphene Heterostructures for Flexible and Multilevel Nonvolatile Photoelectronic Memory.

Author

Liou, Yi-Rou, Lin, Hsia Yu, Shen, Tien Lin, Cai, Shu Yi, Wu, Ya Hsuan, Liao, Yu Ming, Lin, Hung I, Chen, Tzu Pei, Lin, Tai Yuan, and Chen, Yang Fang

Abstract

The development of optical memory with attractive features such as long-lasting, nonvolatile, high-speed, and low-energy consumption is vitally important in the information age. Owing to these advantages, optical memory has been popular for more 10 years. Recently, flexibility has become desirable for the application of wearable devices and smart artificial intelligence; for conventional optical memory, this is still difficult to achieve. To combine optical memory with soft materials, this study presents a flexible and photoelectronic switchable multilevel memory device with long-lasting nonvolatile properties. On the basis of the integration of nanoscale (graphene nanoflakes) and macroscale graphene heterojunctions, a device achieves switchable memory states up to 196 distinct levels under the illumination of lasers with different wavelengths. The photoelectronic memory device can be written optically and erased by both optical and electric methods. Additionally, the device possesses several unique features including a low working bias of 0.5 V, nonvolatility for over 10 000 s, and mechanical stability for more than 10 000 bending cycles. Notably, in previous studies, polymers with poor mobility were used as a conducting channel, which can greatly limit the amplitude of the light-induced switching ratio and electrical performance. In stark contrast, in our device, the graphene layer with the mobility exceeding several orders of magnitude was used to serve as a conducting channel, enabling one to overcome the existing shortcoming. Our approach therefore not only provides an alternative paradigm for the development of photoelectronic memory but also holds great promise for practical applications due to its compatibility with current technologies. [ABSTRACT FROM AUTHOR]

Published
2020
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16. Ultrahigh Sensitive and Flexible Magnetoelectronics with Magnetic Nanocomposites: Toward an Additional Perception of Artificial Intelligence

Author

Cai, Shu-Yi, primary, Chang, Cheng-Han, additional, Lin, Hung-I., additional, Huang, Yuan-Fu, additional, Lin, Wei-Ju, additional, Lin, Shih-Yao, additional, Liou, Yi-Rou, additional, Shen, Tien-Lin, additional, Huang, Yen-Hsiang, additional, Tsao, Po-Wei, additional, Tzou, Chen-Yang, additional, Liao, Yu-Ming, additional, and Chen, Yang-Fang, additional

Published
2018
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17. Breakthrough to Non-Vacuum Deposition of Single-Crystal, Ultra-Thin, Homogeneous Nanoparticle Layers: A Better Alternative to Chemical Bath Deposition and Atomic Layer Deposition

Author

Liao, Yu-Kuang, primary, Liu, Yung-Tsung, additional, Hsieh, Dan-Hua, additional, Shen, Tien-Lin, additional, Hsieh, Ming-Yang, additional, Tzou, An-Jye, additional, Chen, Shih-Chen, additional, Tsai, Yu-Lin, additional, Lin, Wei-Sheng, additional, Chan, Sheng-Wen, additional, Shen, Yen-Ping, additional, Cheng, Shun-Jen, additional, Chen, Chyong-Hua, additional, Wu, Kaung-Hsiung, additional, Chen, Hao-Ming, additional, Kuo, Shou-Yi, additional, Charlton, Martin, additional, Hsieh, Tung-Po, additional, and Kuo, Hao-Chung, additional

Published
2017
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18. Highly Reliable and Sensitive Tactile Transistor Memory

Author

Chen, Chien-Tung, primary, Lee, Wen-Ya, additional, Shen, Tien-Lin, additional, Wu, Hung-Chin, additional, Shih, Chien-Chung, additional, Ye, Bo-Wei, additional, Lin, Tzu-Yao, additional, Chen, Wen-Chang, additional, and Chen, Yang-Fang, additional

Published
2017
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19. Bridging the “green gap” of LEDs: giant light output enhancement and directional control of LEDs via embedded nano-void photonic crystals

Author

Tsai, Yu-Lin, primary, Liu, Che-Yu, additional, Krishnan, Chirenjeevi, additional, Lin, Da-Wei, additional, Chu, You-Chen, additional, Chen, Tzu-Pei, additional, Shen, Tien-Lin, additional, Kao, Tsung-Sheng, additional, Charlton, Martin D. B., additional, Yu, Peichen, additional, Lin, Chien-Chung, additional, Kuo, Hao-Chung, additional, and He, Jr-Hau, additional

Published
2016
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20. Accelerating dynamic peak power analysis using an essential-signal-based methodology

Author

Hermes Lin, Jing-Yang Jou, Shen-Tien Lin, Che-Hua Shih, and Chia-Chih Yen

Subjects
Reduction (complexity), Power analysis, Speedup, law, Computer science, Low-power electronics, Real-time computing, Integrated circuit, Algorithm, Signal, law.invention, Power (physics), Network analysis
Abstract

Accurate peak power measurement requires detailed switching and delay information for each signal over the entire simulation. Performing a full signal dump and power calculation for a long simulation run usually spends a large amount of time and disk space. In this paper, we propose an Essential-signal-based methodology which only performs power analysis over a small subset of the original simulation but still acquires the true peak power value. Experimental results show that the proposed methodology significantly decreases both time (about 18 X speedup) and disk space usage (about 87% reduction) against the traditional power analysis flow.

Published
2011

22. Software-enabled design visibility enhancement for failure analysis process improvement

Author

Chia-Chih Yen, Etienne Auvray, Kai Yang, Paul Gibson, Jerome Peillat, and Shen-Tien Lin

Subjects
Engineering, Software, business.industry, Process (engineering), Embedded system, Visibility (geometry), Electronic design automation, CAD, Solid modeling, Tracing, business, AND gate
Abstract

Traditional failure analysis (FA) process proceeds by investigating the tester results of several suspected silicon signals, and then applying CAD tools to navigate and compare pre-silicon design behaviors. However, existing CAD tools usually lack of design visibility due to the imperfect link between test and design environments. In this paper, we introduce a series of design visibility enhancement tools to augment FA process flow. These tools not only feature design comprehension and logic tracing capability, but also expand and correlate silicon data to design functionality. With the seamless visibility enhancement environment, we show the FA process can be performed more efficiently.

Published
2009

23. Embedded memory diagnostic data compression using differential address

Author

Yeong-Jar Chang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Wen-Ching Wu, and Rei-Fu Huang

Subjects
Scheme (programming language), business.industry, Computer science, Design for testing, Process (computing), Chip, Built-in self-test, Embedded system, Transmission time, business, computer, computer.programming_language, Data compression, Volume (compression)
Abstract

Embedded memory diagnostics is normally done by the built-in self-diagnosis (BISD) hardware, which collects and sends the diagnostic data to the external tester. The cost of the diagnosis process highly depends on the data volume sent between the chip under test and the tester, since the transmission time and the tester capture memory are major cost factors. We propose a memory BISD design using differential addressing, as well as a method for evaluating and choosing a proper differential address level. Based on our previous work on pattern identification BISD and syndrome compression design, the proposed differential address compression scheme further reduces the diagnostic data volume. Experimental results show that the BISD design is cost-effective.

Published
2005

24. Fail Pattern Identification for Memory Built-In Self-Repair

Author

Rei-Fu Huang, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Chin-Lung Su, and Yeong-Jar Chang

Subjects
Engineering, Built-in self-test, business.industry, Spare part, Embedded system, Overhead (computing), Memory rank, System on a chip, Hardware_PERFORMANCEANDRELIABILITY, Integrated circuit design, Memory refresh, business, Memory controller
Abstract

With the advent of deep submicron technology and system-on-chip (SOC) design methodology, we are seeing on-chip memory cores to represent a growing percentage of the chip area. The yield of an SOC is usually dominated by the memory yield, so the improvement of memory yield is crucial in SOC development. In this work, we propose a built-in self-repair (BISR) scheme for memory yield improving. The novelty of our approach is that we can identify the fail patterns so that appropriate spare elements (e.g., spare rows, columns, words, or blocks) can be allocated to repair the defective memory. Some BISR methods are discussed and compared. We select the scheme that uses fewer spare elements than others given the same repair rate. The area overhead of the BISR scheme is only 2.2% for an 8K/spl times/64 memory.

Published
2005

25. A testable BIST design for PLL

Author

Kun-Lun Luo, Wen-Ching Wu, Yeong-Jar Chang, and Shen-Tien Lin

Subjects
Engineering, business.industry, Design for testing, Subtraction, Hardware_PERFORMANCEANDRELIABILITY, Automatic test pattern generation, Phase-locked loop, Reliability (semiconductor), Built-in self-test, Fault coverage, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, business, Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION, Jitter
Abstract

We present a testable built-in self test(BIST) design for phase-lock loop(PLL). The design can measure the clock jitter for PLL with high precision and high accuracy due to better utilization of the test integration and test subtraction techniques. Although the BIST circuit is implemented by all digital standard cells to achieve better reliability, it can even be applied to measure the analog clock jitter. Besides, for some DfT (design for test) techniques inserted to make BIST itself testable, we discuss the trade-off among area, timing, number of test patterns and fault coverage in this paper.

Published
2004

31. Ultrahigh‐Performance Self‐Powered Flexible Photodetector Driven from Photogating, Piezo‐Phototronic, and Ferroelectric Effects.

Author

Shen, Tien‐Lin, Chu, Yu‐Wei, Liao, Yu‐Kuang, Lee, Wen‐Ya, Kuo, Hao‐Chung, Lin, Tai‐Yuan, and Chen, Yang‐Fang

Subjects
*FERROELECTRICITY, *FERROELECTRIC polymers, *FERROELECTRIC thin films, *PHOTODETECTORS, *OPTOELECTRONIC devices, *INTERNET of things, *ELECTRIC fields
Abstract

Owing to the need for dynamic, real‐time, and on‐site data collection in internet of things applications, the realization of ultra‐sensitive sensing networks with self‐powered, flexible, and lightweight devices has become an important issue for the development of sensor systems. In this work, a novel, high‐performance, self‐powered photodetector is achieved through the combination of photogating, piezo‐phototronic, and ferroelectric effect by incorporating a ferroelectric thin film of poly(vinylidene fluoride‐co‐trifluoroethylene) in a rationally designed device structure with suitable band alignment, which can modulate carrier transport behavior at the interface due to the internal electric field produced by light illumination, external strain, or voltage‐poled dipole. This enables photocurrent and overall device performance to improve significantly. The unprecedented photodetector presented in this study has several merits, including mechanical flexibility and light weight that allow it to adapt to arbitrary surface topology; additionally, its self‐powering capability and high reliability are urgently needed for the demanding functionality of devices for the development of next‐generation optoelectronic devices, spanning from wearable communication to unattended harsh environments with a human‐friendly interface. [ABSTRACT FROM AUTHOR]

Published
2020
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