249 results on '"Shen-Fu Hsiao"'
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2. Neural Network Acceleration Using Digit-Plane Computation with Early Termination.
3. Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination.
4. A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture.
5. A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.
6. Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation.
7. Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning.
8. Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation.
9. Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations.
10. Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication.
11. Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse.
12. Low-Complexity Deep Neural Networks for Image Object Classification and Detection.
13. Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks.
14. Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations.
15. Optimization of Lookup Table Size in Table-Bound Design of Function Computation.
16. Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks.
17. Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels.
18. Hardware design of disparity computation for stereo vision using guided image filtering.
19. Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage.
20. Quantization of Deep Neural Network Models Considering Per-Layer Computation Complexity for Efficient Execution in Multi-Precision Accelerators.
21. Efficient Computation of Depthwise Separable Convolution in MoblieNet Deep Neural Network Models.
22. Hierarchical Multipartite Function Evaluation.
23. Low-power and high-performance design of OpenGL ES 2.0 graphics processing unit for mobile applications.
24. An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support.
25. Hardware design of histograms of oriented gradients based on local binary pattern and binarization.
26. Low-power dual-precision table-based function evaluation supporting dynamic precision changes.
27. Design of low-leakage multi-port SRAM for register file in graphics processing unit.
28. VLSI implementation of belief-propagation-based stereo matching with linear-model message update.
29. Compression of Lookup Table for Piecewise Polynomial Function Evaluation.
30. Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning.
31. VLSI implementations of stereo matching using Dynamic Programming.
32. Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units.
33. Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators.
34. Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling.
35. Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system.
36. Low-cost designs of rectangular to polar coordinate converters for digital communication.
37. Designs of angle-rotation in digital frequency synthesizer/mixer using multi-stage architectures.
38. A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation.
39. Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method.
40. Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation.
41. An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches.
42. Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.
43. Efficient designs of flaoting-point CORDIC rotation and vectoring operations.
44. Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation.
45. Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding.
46. An Automatic Cache Generator Based on Content-Addressable Memory.
47. Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.
48. An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.
49. Hardware efficient implementation of histograms of oriented gradients for pedestrian detection.
50. Partition methodology for the final adder in a tree-structure parallel multiplier generator.
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