Search

Advancements in electronic technology have led to the emergence of portable devices like smartphones and smartwatches. For these devices, low-power supply management systems are crucial. In this study, the LDO (low-drop) regulator is implemented with TSMC 0.18 um CMOS high-voltage process. This chip is designed based on multi-current mirror circuits to implement a level-shifting circuit for controlling the error amplifier. The new architecture is achieved using the structure of three low-voltage operational amplifiers. The gate voltage of the power transistor is precisely driven by the level-shifting circuit, eliminating the need for a voltage limiting circuit on the power MOS's Vgs, thus enhancing the response time. This chip incorporates a temperature protection circuit that controls the feedback circuit for high-voltage MOS components. When the temperature exceeds a predefined threshold, the output shuts down immediately. Experimental results demonstrate that this chip can output voltages ranging from 3 to 19 V when the input voltage ranges from 3.5 to 20 V. The chip achieves a maximum output current of 1A and a peak conversion efficiency of 89.94%. [ABSTRACT FROM AUTHOR]

The aim of this paper is to distinguish the vehicle detection and count the class number in each classification from the inputs. We proposed the use of Fuzzy Guided Scale Choice (FGSC)-based SSD deep neural network architecture for vehicle detection and class counting with parameter optimization. The 'FGSC' blocks are integrated into the convolutional layers of the model, which emphasize essential features while ignoring less important ones that are not significant for the operation. We created the passing detection lines and class counting windows and connected them with the proposed FGSC-SSD deep neural network model. The 'FGSC' blocks in the convolution layer emphasize essential features and find out unnecessary features by using the scale choice method at the training stage and eliminate that significant speedup of the model. In addition, FGSC blocks avoided many unusable parameters in the saturation interval and improved the performance efficiency. In addition, the Fuzzy Sigmoid Function (FSF) increases the activation interval through fuzzy logic. While performing operations, the FGSC-SSD model reduces the computational complexity of convolutional layers and their parameters. As a result, the model tested Frames Per Second (FPS) on edge artificial intelligence (AI) and reached a real-time processing speed of 38.4 and an accuracy rate of more than 94%. Therefore, this work might be considered an improvement to the traffic monitoring approach by using edge AI applications. [ABSTRACT FROM AUTHOR]

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ. [ABSTRACT FROM AUTHOR]

The application and integration of the power IC chip is more and more important for electronic devices. In this study, we develop high-voltage buck-boost conversion chip. Based on auto mode switch, this chip can achieve a stable output voltage without the need of detecting input level. The proposed technique can automatically adjust the on-time value using discharged loop to rapidly shorten the transient response time. The system could always maintain steadily the output voltage of 24V as the range of input voltage is widely from 12V to 40V. The output load current is available from 20 ​mA to 1A, and the highest transform efficiency is 86.3%. As the load current is suddenly changed from high to low, the overshoot level can be reduced with a fast discharging loop, and to fasten the transient speed. As for the low-voltage conversion, it outputs 3.3V under the input from 2.5V to 5V, where the maximum efficiency of buck/boost can achieve 94%. The chip is implemented TSMC0.25 ​ μ m HV- process, and the size of the circuit layout is 2.18 ​mm2, where four power MOS had been integrated to the chip for buck-boost control. [ABSTRACT FROM AUTHOR]

A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node. [ABSTRACT FROM PUBLISHER]

A novel low‐power sense‐amplifier‐based flip‐flop (FF) is presented. Using a simplified single‐ended pass transistor‐based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense‐amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive post‐layout simulations. [ABSTRACT FROM AUTHOR]