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A comprehensive quantum anisotropic transport model for holes is used to study silicon PMOS inversion layer transport under arbitrary stress. The results have shown that the hole band structure is dominated by 12 'wings,' where mechanical stress, as well as the vertical field under certain stress conditions, alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility.

A 90-nm generation logic technology designed for high speed and low power operation is described. Strained-Si is added using a novel process flow for significant mobility enhancement.

In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node dimensions using ensemble Monte Carlo simulations. It is found that due to large external resistance, lack of stressing methods, smaller bandgap, larger dielectric constant, and increased variability that in the absence of major innovation, Ge is not an ideal candidate for channel replacement material of pMOS in future CMOS technology generation FinFETs. In order for Ge to compete with Si, it would at a minimum require a stressing mechanism and improved contact resistance, but leakage and variability would still be a concern for low-power applications. [ABSTRACT FROM AUTHOR]

A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a two-dimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 ‘wings,’ where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility. [ABSTRACT FROM AUTHOR]

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology [1]. Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si1-xGex in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSEFT. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work, 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies. [ABSTRACT FROM AUTHOR]