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Dominant time constant analysis reveals that the semiconductor equations at hard breakdown turn into a positive feedback state where the convergence of steady state (DC) Newton iteration is substantially difficult even if continuation method is used. A robust simulation method for hard breakdown which detects the appearance of negative time constant during DC Newton iteration and then switches to transient (TR) simulation is proposed. The negative time constant value during the TR simulation is used for the time step restriction and the maximum time constant value is used for the determination of the final time of the TR simulation. By using the proposed method, a trace of the stable operation points in the snapback I-V trajectory corresponding to each DC bias can be obtained robustly with a simple voltage sweep at the voltage boundary.

A variation-tolerant and radiation-hardened flip-flop in a 16-nm FinFET technology called Bistable Cross-coupled Dual-Modular-Redundant Flip-Flop (BCDMR FF) was fabricated, which is an improvement on the BCDMR in 65 nm bulk. The 16 nm BCDMR FF exhibits cross sections below 1e-11 cm2/FF at 0.8 V by Ag ions, which is 1/100 and 1/4,000 smaller than a conventional DFF in 16-nm FinFET and 65-nm planer processes respectively. With this low cross-section the BCDMR FF can be used for highly reliable and high performance systems.

A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90 nm- and 65 nm-CMOS technologies having the channel orientations of, respectively, (110) and (100), both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8 mV for the threshold voltage, as opposed to ∼20% and ∼50 mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

We have developed a surface-potential-based metal–oxide–silicon (MOS)-varactor model valid for RF applications up to 200 GHz. The model enables the calculation of the MOS-varactor capacitance seamlessly from the depletion region to the accumulation region and explicitly considers the carrier-response delay causing a non-quasi-static (NQS) effect. It has been observed that capacitance reduction due to this non-quasi-static effect limits the MOS-varactor application to an RF regime.

The effect of the inversion layer quantization for metal-oxide-semiconductor field-effect transistors (MOSFETs) under off-current as well as on-current condition is investigated by simulation. The main focus is given for MOSFETs with an optimized pocket profile. It is shown that the optimized pocket profile for gate length down to 70 nm MOSFET causes an enhancement of the threshold voltage increase with reducing gate length. This is due to the effective impurity-concentration increase caused by the pocket implantation, while the quantum effect itself is weakened by the short-channel effect. Though the quantum effect weakens from source to drain due to the short-channel effect under on-current condition, its strength at source determines the whole MOSFET performance for the gate length down to 70 nm. This was confirmed by Monte Carlo simulation including the quantum effect by an effective potential method.

A new test structure which can provide voltage to the very narrow source/drain region between adjacent gates by drawing out the source/drain silicide layer has been developed. By using the test structure, the dependence of the gate-drain capacitance (Cgd) on the gate-gate space (Lsp) has been successfully measured until the minimum gate pitch where no contact can be placed. Decrease of Cgd with respect to the decrease of Lsp has been observed and its main cause is identified as the decrease of the gate-drain overlap length.

Neutron induced single event transient (SET) has been measured on NAND and inverter (INV) chain with changing fan-out, drive strength, size of drain diffusion area, temperature and VDD on 40nm and 90nm bulk CMOS technology. As the pulse width distribution varies with the length of SET target chain as well, it is important to use the chain length similar with the actual logic circuits. Using tens of stages of target chain, pulses wider than 150ps have been rarely observed. The results of the measurement show that the SER of SET changes depending on the cell type and fan-out. SER of SET in combinational logic circuits decreases by half from 90nm to 40nm for the same gate count and the same clock frequency.

A sine-wave noise generator with a harmonic-eliminated waveform is proposed for measuring the noise tolerance of analog IPs. In the waveform, harmonics up to the thirteenth harmonic are eliminated by combining seven rectangular waves with 22.5-degree spacing phases. This waveform includes only high-region frequency harmonic components which are easily suppressed by a low-order filter. In the circuit, the harmonic-eliminated waveform generator is combined with a current-controlled oscillator and a frequency-adjustment circuit. The sine-wave noise generator can generate power-line noise from 20 MHz to 220 MHz in 1 MHz steps. A spurious-free dynamic range (SFDR) of 45 dB is obtained at the 100 MHz noise frequency.

In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, V th , of 1.0-V transistors in a 90-nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC response of the same amplifier. The distribution of AC gain versus V th of transistors within amplifiers is captured. The degradation of common-mode rejection property is observed for an amplifier with intentionally introduced mismatches to the pair of transistors.

A novel SET pulse measurement circuit is proposed which can detect pulses narrower than 100ps. Alternation of SET pulses during the propagation through the chain of target cells is minimized, which is attributed to small chain length (typically 20). This circuit configuration contributes to obtaining pulse distribution similar to that observed in actual circuit in use. Distribution of SET pulse width measured by our circuit through the white neutron beam testing agrees well with that estimated by computer simulation.

A discrete surface potential model which accurately reflects channel doping profile is proposed. The proposed model is an improvement from the previously proposed model (1) in order to accurately calculate drain current in full bias region using the same mobility and velocity saturation models as TCAD. Since the proposed model is a kind of first-principal-compact- model without any unphysical fitting parameters, it can become micro-TCAD which is a by far faster and lighter substitute for conventional TCAD. As an application of the proposed model, ultra-fast calculation of threshold voltage variation induced by random dopant fluctuation using Monte-Carlo method is introduced.

A new approach for improving physical scalability of existing compact models is proposed. The behavior of internal BSIM4 model parameters in response to a change in fabrication process condition is modeled by physics-based meta-model equations. By recovering missing links between the fitting parameters and device design parameters, the model parameter sets for variant transistors with different channel implant dose can be predicted starting from a parameter set of existing reference transistors.

Current responses due to the strike of ionized particle onto nMOS transistor of 90nm and 55nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (tcc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between tcc values of 90nm and 55nm generation MOSFETs have been investigated and it is found that the difference in STI depth and width of p-well contact line between these two generations influences tcc mainly. This is because that the resistance below the p-well contact affects the ability to pull out the excess holes remaining in the channel region. It is also shown that there is room for reducing tcc and hence SET pulse width by well profile engineering. I. INTRODUCTION Neutron-induced soft error phenomena have received much attention since they are considered as one of the major ob- stacles to realize highly reliable LSIs. Although Single-Event- Upset observed in memory circuits such as SRAMs and flip- flops is still major concern, soft error phenomena occurring in combinational-logic circuits can be more serious in future technology node (1). In the logic circuits, propagation of erroneous signal, called Single-Event-Transient (SET), occurs and the erroneous signal might be finally stored, for instance, in a flip-flop as illustrated in Fig. 1. The wider the SET pulse is, the more probably the erroneous signal is stored. Such a SET pulse is initially caused by collection of generated charge due to the impact of the ionized particle. In this paper, duration of charge collection is evaluated which is related to SET pulse width strongly, and its dependence on device structure dimensions and profiles is investigated.

An on-chip sampling oscilloscope with lps timing resolution is realized in 90nm CMOS process based on a proposed ramp waveform division scheme for precise signal integrity and power-line integrity measurement. The resolution in time is variable from 1ps to 64ps in 64 steps. A novel on-chip inductance measurement procedure is also proposed

An automatic Delaunay partitioned mesh generation which is effective in reduction of numerical errors in a diffusion process near the interface or in the thin layer is proposed. An interface protection layer which consists of a rectangular mesh locally conformed to a material interface is introduced. A validity of the interface protection layer for avoiding an artificial threshold voltage shift of about 1 V due to a boron penetration through a pMOS gate oxide is demonstrated.

Accurate global modeling is a key issue for the successful application of TCAD to the ULSI device design solution. To demonstrate how far we can go with the state-of-the-art global modeling, we tried to design 0.13 [/spl mu/m] CMOS device by using our globally calibrated advanced process/device models. This paper reports the design methodology and the results compared with the fabricated device characteristics.

A systematic and physically based method for extracting of a unified parameter set for a point-defect diffusion model is proposed. A sensitivity matrix analysis is used to construct the sequence of the extraction and to select the data set to be fitted.