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166 results on '"Shim, Tae-Hun"'

10. Super‐Linear‐Threshold‐Switching Selector with Multiple Jar‐Shaped Cu‐Filaments in the Amorphous Ge 3 Se 7 Resistive Switching Layer in a Cross‐Point Synaptic Memristor Array

Author

Kim, Hea‐Jee, primary, Woo, Dae‐Seong, additional, Jin, Soo‐Min, additional, Kwon, Hyo‐Jun, additional, Kwon, Ki‐Hyun, additional, Kim, Dong‐Won, additional, Park, Dong‐Hyun, additional, Kim, Dong‐Eon, additional, Jin, Hong‐Uk, additional, Choi, Hyun‐Do, additional, Shim, Tae‐Hun, additional, and Park, Jea‐Gun, additional

Published
2022
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25. Design of Ag–Ga–S2-xSex-based eco-friendly core/shell quantum dots for narrow full-width at half-maximum using noble ZnGa2S4shell material

Author

Lee, Seung-Jae, Lee, Ji-Eun, Lee, Chang-Jin, Jeong, Ui-Hyun, Lee, Woo-Guk, Kwon, Hyo-Jun, Kim, Min-Won, Shim, Tae-Hun, and Park, Jea-Gun

Abstract

I–III–VI-based quantum dots (QDs) are promising eco-friendly light-emitting materials for next-generation displays. Thus far, I–III–VI-based QDs (i.e., AgIn1-xGaxS2) are still insufficient as light-emitting materials for display fields because of their deteriorated optical properties caused by lattice mismatch between the core/shell materials. We designed a novel passivation process using a shell material (i.e., ZnGa2S4) with crystalline structure identical to that of AgGaS2-xSexcore QDs (tetragonal). Green and red light-emitting AgGaS2/ZnGa2S4core/shell QDs demonstrated superior optical properties owing to the minimum lattice mismatch between the AgGaS2-xSe2core and ZnGa2S4shell materials. In particular, a higher quantum yield (QY) and narrow full-width at half-maximum (FWHM) for the green and red light-emitting QDs were achieved, i.e., QYs of 69% and 64% and FWHMs of 26 and 28 nm, respectively. In addition, this remarkable enhancement of optical properties resulted in an increase of ~ 94.4% in the color-space agreement with ITU-R recommendation BT.2020. This means that AgGaS2-xSex-based core/shell QDs have the potential to be used as eco-friendly QDs for light-emitting materials in next-generation displays.

Published
2022
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36. Design of n+-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector.

Author

Lee, Byoung-Seok, Kim, Min-Won, Kim, Ji-Hun, Yoo, Sang-Dong, Shim, Tae-Hun, and Park, Jea-Gun

Subjects
THYRISTORS, TISSUE arrays, MEMORY, EPITAXIAL layers, CELL size
Abstract

The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (Ion/Ioff) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ˝ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption). [ABSTRACT FROM AUTHOR]

Published
2021
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41. Sputter‐grown GeTe/Sb2Te3 superlattice interfacial phase change memory for low power and multi‐level‐cell operation.

Author

Jin, Soo‐Min, Kang, Shin‐Young, Kim, Hea‐Jee, Lee, Ju‐Young, Nam, In‐Ho, Shim, Tae‐Hun, Song, Yun‐Heub, and Park, Jea‐Gun

Subjects
SPUTTERING (Physics), PHASE change memory, SEMICONDUCTOR storage devices, SUPERLATTICES, SPUTTER deposition
Abstract

The multi‐level feature of GeTe/Sb2Te3 interfacial phase change memory was achieved by applying a designed voltage‐based pulse. It stably demonstrated five multi‐level states without interference for 90 cycles by varying the pulse width. GeTe/Sb2Te3 interfacial phase change memory demonstrated retention time of > 1.0 × 103 s, presenting the significantly low drift coefficient (ν) of < 0.009, indicating no resistivity drift due to the structure relaxation of glass. In addition, the reset energy consumption of GeTe/Sb2Te3 interfacial phase change memory was reduced by more than 85% compared to conventional Ge2Sb2Te5 phase change memory at each bottom electrode contact size. Multi‐level‐cell operation mechanism and gradual increase in conductance value of GeTe/Sb2Te3 interfacial phase change memory was explained by a partial resistance transition model where phase transition occurred partially in all layers. The result of the GeTe/Sb2Te3 interfacial phase change memory performance is expected to bring great advantages to the next‐generation storage class memory industry that requires low energy and high density. [ABSTRACT FROM AUTHOR]

Published
2022
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49. Dependence of temperature and self-heating on electron mobility in ultrathin body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors.

Author

Shim, Tae-Hun, Kim, Seong-Je, Lee, Gon-Sub, Kim, Kwan-Su, Cho, Won-Ju, and Park, Jea-Gun

Subjects
*PARTICLES (Nuclear physics), *FREE electron theory of metals, *FIELD-effect transistors, *ELECTRONICS, *ELECTRON mobility
Abstract

We investigated the dependence of temperature and self-heating on electron mobility in ultrathin body fully depleted silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors as a function of silicon thickness by analyzing their electron states and electrical characteristics. We found that as the temperature increases, electron mobility decreases regardless of the silicon thickness. We also found that there is a less decrease when the silicon thickness is less than 3 nm than when it is greater than 3 nm. This is because there is a greater electron occupancy in a twofold valley. We demonstrated that the quantum size-effect, i.e., the higher electron mobility in silicon with a thickness less than 3 nm caused by the size-effect, can be eliminated by self-heating. [ABSTRACT FROM AUTHOR]

Published
2008
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50. Impact of the top silicon thickness on phonon-limited electron mobility in (110)-oriented ultrathin-body silicon-on-insulator n-metal-oxide-semiconductor field-effect transistors.

Author

Moon, Hui-Chang, Kim, Seong-Je, Shim, Tae-Hun, and Park, Jea-Gun

Subjects
FIELD-effect transistors, METAL oxide semiconductors, PHONONS, ELECTRON mobility, SILICON
Abstract

We investigated through a theoretical simulation how the phonon-limited electron mobility in both (110)- and (100)-oriented ultrathin-body (UTB) silicon-on-insulator (SOI) n-metal-oxide-semiconductor field-effect transistors (MOSFETs) depends on the top silicon thickness within a range from 20 to 2 nm. No electron mobility enhancement was observed in (110) UTB SOI n-MOSFETs when the top silicon thickness was around 5 nm, unlike in (100) UTB n-MOSFETs. Thus, electron mobility in (110) UTB SOI n-MOSFETs decreased with top silicon thickness, particularly in the range below 10 nm. We attributed the electron mobility degradation in (110) UTB SOI n-MOSFETs within the top silicon thickness range below 10 nm to a decrease in the effective width of the inversion layer and an increase in intravalley acoustic phonon scattering, rather than to less carrier repopulation due to less band splitting between two- and fourfold valleys. [ABSTRACT FROM AUTHOR]

Published
2007
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