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Active leakage current is much larger (∼10×) than standby leakage current, and takes a large proportion (30% to 40%) of active power consumption. Active mode power gating (AMPG) has been proposed to extend the application of basic power gating to reducing active leakage; it relies on clock-gating signals to cut the power off a part of combinational gates. The problem to select those gates while integrity of circuit behavior remains intact has not been solved yet. We identify three constraints to solve this problem, namely functional, timing, and current constraints. The problem of synthesizing AMPG circuits is then laid out, and synthesis algorithm is proposed; a group of gates that can be power-gated by each clock-gating signal and the size of footer that is attached to the group constitute a synthesis output. The layout methodology for standard cell designs is proposed to assess AMPG circuits in area and wirelength. Experiments in 1.1 V, 45-nm technology demonstrate that active leakage is reduced by 16% on average compared to clock-gated circuits. [ABSTRACT FROM AUTHOR]