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Summary An analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs. [ABSTRACT FROM AUTHOR]

In this paper, based on reversibility and approximation concepts, full adder (FA) circuits are designed for fault-tolerant applications. Area saving along with power reduction is the main objectives in the design and implementation of the proposed FAs. So, the basic reversible gates including Toffoli, Fredkin, Feynman, and Thapliyal Ranganathan (TR) are realized based on the gate diffusion input (GDI) technique. Subsequently, three approximate reversible FAs are designed with 3, 2, and 1 gates, respectively, which have special features such as 0 constant input (CI) and minimum garbage output and transistor counts. The circuitry performance and the quality of output images are extracted, when the FAs are placed in the approximate ripple carry adder (RCA) for image addition. The results show the superiority of the proposed FAs. Comprehensive results are extracted from the defined figure of merits (FoMs), which consists of area, power-delay product (PDP), peak signal-to-noise ratio (PSNR), and normalized mean error distance (NMED). The Pro-2 FA is selected as the best option due to its significant superiority compared to other circuits. The Pro-2 has 61.47% and 73.51% savings of PDP and PDP-area product (PDAP), respectively, compared to the exact circuit. [ABSTRACT FROM AUTHOR]

An adaptive neuro‐fuzzy inference system is presented which is optimized by a genetic algorithm to classify normal and abnormal brain tumours. The classifier is fast and simple, named genetic algorithm‐adaptive neuro‐fuzzy inference system, and the determined learning rules minimize its error and improve its accuracy. The presented system follows five steps including preprocessing, morphological operation, feature extraction, feature selection, and classification. Morphological operators segment the abnormal regions and calculate the tumour area. The statistical features and the grey‐level co‐occurrence matrix are employed for feature extraction. Magnetic resonance images are considered and 12 statistical features are extracted, then the genetic algorithm‐based selection technique helps to select features and reduce the extracted features and improves the accuracy and decision time. So, the high dimensionality and the computational complexity of the adaptive neuro‐fuzzy inference system are reduced, and the classifier decides more efficiently. The input data are the figshare brain tumour dataset with 670 abnormal and 670 normal magnetic resonance images, and the classifier requires 10.788 s for classification. The efficient performance of the genetic algorithm‐adaptive neuro‐fuzzy inference system is confirmed by the accuracy of 99.85%, sensitivity of 99.7%, specificity of 100%, precision of 100%, and mean square error of 0.0027. [ABSTRACT FROM AUTHOR]

Summary A ripple carry adder (RCA) structure is presented which can concurrently correct a gain error in low‐resolution pipeline analog‐to‐digital converters (ADCs). The RCA is composed of a new swing‐boosted full adder (FA) based on the transmission gate (TG) technique. So, it is low‐power, high‐speed, and full‐swing with high driving capability. In 90 nm technology, the results of power, delay, and power‐delay‐product (PDP) of the FA are 1.5296 μW, 2.1141 ns, and 3.2337 fJ, respectively. The RCA with an area of 408.09 μm2 is evaluated by a 3‐bit pipeline ADC with 1.5‐bit per stage. When the erroneous codes are passed through the RCA, the maximum and minimum integral nonlinearity (INL) are improved by 19.83% and 90.98%, while the maximum and minimum of the differential nonlinearity (DNL) are improved by 50%, and 42.06%, respectively. [ABSTRACT FROM AUTHOR]

Magnetic resonance imaging (MRI) is a high‐quality medical image that is used to detect brain tumours in a complex and time‐consuming manner. In this study, a back propagation neural network (BPNN) along with the Levenberg–Marquardt algorithm (LMA) is proposed to classify MRIs and diagnose brain tumours in a simple and fast process. The BPNN has 10 neurons in the hidden layer, and the default function of the feedforward feeds is mean squared error (MSE). The LMA is optimized as a multivariable adaptive approach and considerably decreases the MSE of the BPNN, so the errors of the tumour classification are diminished. The proposed method follows four steps including preprocessing, skull removal, feature extraction, and classification. The input MRIs are converted to greyscale, resized, and thresholding is performed in the preprocessing step and followed by skull removal. Morphological operations of closing, opening, and dilation are used to segment abnormal areas in the MRIs, and the opening operator recognizes the tumour more accurately. Using statistical analysis and a grey‐level co‐occurrence matrix (GLCM) 12 features are extracted from the MRIs and used as the inputs of the BPNN. To evaluate the proposed method, 670 normal and 670 abnormal brain MRIs are used as input data, and the classification is performed in 0.494 s. The accuracy, sensitivity, specificity, precision, dice, recall, and MSE are 98.7%, 97.61%, 99.7%, 97.61%, 98.6%, 97.61%, and 0.005, respectively. The approach is accurate and fast for medical images classification. [ABSTRACT FROM AUTHOR]

A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs. [ABSTRACT FROM AUTHOR]

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

Summary: The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs. [ABSTRACT FROM AUTHOR]

This paper presents a low-temperature coefficient (TC) dual-reference CMOS bandgap reference (BGR) for high-performance systems working under a wide temperature range. It consists of a correction approach to eliminate the high-order inaccuracy, in which an enhanceable curvature compensation circuit is adopted to extend the operating temperature range and generate reference voltages with sub-1 ppm/°C TC. In addition, a voltage level shifter (VLS) is used to generate the latter compensated reference voltage but no need for an additional compensation circuit. The proposed BGR designed in a 0.18-µm CMOS process has a simulated TC of 0.75 ppm/°C and 0.28 ppm/°C for the first and second reference outputs, respectively, over a wide temperature range of −50 °C to 130 °C. The proposed BGR occupies a 0.0079-mm2 silicon area. The overheads make the BGR appropriate to provide reference voltages in diverse chips with high-precision systems. [ABSTRACT FROM AUTHOR]

A new 12-transistor reversible full adder (FA) is designed based on carbon-nanotube-field effect transistors (CNTFETs) with 32 nm channel length and an area of 0.2204 μm2, 1 constant input (CI), and 3 garbage outputs (GO). The FA has 3 reversible logic gates in two of its stages that are realized by the gate diffusion input (GDI) technique. In the FA, 2 Toffoli gates with 1 CI and 1 new GDI-reversible-multiplexer are used to generate Sum and C out , respectively. The multiplexer is 3*3, with two GOs, and a significant area reduction by only two transistors. The inputs of the circuit prevent the excessive increase of GOs and CIs. The Monte Carlo analysis using the HSPICE simulator indicates a better sensitivity of the FA versus fabrication with 6.45%, 1.86%, and 8.01% improvements of maximum values of power, delay, and power-delay-product (PDP). The FA is implemented in a 4-bit, 8-bit, 16-bit, and 32-bit ripple carry adder (RCA), and its superior results are seen. Under 32-bit RCA, the proposed circuit with 4956.30 fJ shows more energy savings compared to most competitors. The extracted results, the different figure of merits (FoMs), and reversibility features represent the proposed circuit as a desirable procedure for future works. [ABSTRACT FROM AUTHOR]

Brain tumour detection is still a challenging problem both in medical and image processing. In this study, two scenarios are applied to diagnose human brain tumours, classical image processing (CIP) and a new algorithm called binary image with variable fuzzy level (BIVFL). Magnetic resonance imaging (MRI) process from the BraTs 2019 database. Edge detection and prognosis area cropping are parts of the high‐computational CIP algorithm. For the CIP, the best filter is the combination of the horizontal and vertical modes of the Prewitt filter. In the BIVFL, by changing the fuzzy level for binarisation images two clusters are filled with tumour and no tumour areas, and the tumour area is extracted in various accuracies. Sensitivity, specificity, precision, and accuracy of the BIVFL are varied according to the fuzzy level, and the best value of sensitivity is 0.9, but the value of three other parameters is 1 for an interval of fuzzy levels. The BIVFL is a simple and fast tumour area extraction algorithm, and also it is easy to implement with digital signal processors. Histogram and power signal‐to‐noise ratio of the BIVFL is remarkable. [ABSTRACT FROM AUTHOR]

Brain tumour detection is still a challenging problem both in medical and image processing. In this study, two scenarios are applied to diagnose human brain tumours, classical image processing (CIP) and a new algorithm called binary image with variable fuzzy level (BIVFL). Magnetic resonance imaging (MRI) process from the BraTs 2019 database. Edge detection and prognosis area cropping are parts of the high-computational CIP algorithm. For the CIP, the best filter is the combination of the horizontal and vertical modes of the Prewitt filter. In the BIVFL, by changing the fuzzy level for binarisation images two clusters are filled with tumour and no tumour areas, and the tumour area is extracted in various accuracies. Sensitivity, specificity, precision, and accuracy of the BIVFL are varied according to the fuzzy level, and the best value of sensitivity is 0.9, but the value of three other parameters is 1 for an interval of fuzzy levels. The BIVFL is a simple and fast tumour area extraction algorithm, and also it is easy to implement with digital signal processors. Histogram and power signal-to-noise ratio of the BIVFL is remarkable. [ABSTRACT FROM AUTHOR]

Size reduction in complementary metal–oxide–semiconductor integrated circuits (ICs) is a challenge. Carbon nanotube field effect transistor (CNTFET) technology with advantages such as low power, high mobility, and ballistic transmissions is an alternative. Based on the standard 32 nm CNTFET technology, a new 23-transistor full adder cell is proposed with combining advantages of gate diffusion input and transmission gate techniques, which are low power and full swing. Owing to small number of transistors and internal nodes, the delay time and activity factor decreased to 13.5τ. Simulations of critical parameters variations like VDD, temperature, and fan-out expose better performance of the proposed cell. Investigating the process voltage temperature with Monte Carlo simulation verified better stability, immunity, and tolerability of the cell in comparison with well-known full adder cells. Suggested full adder cell was implemented in 4:2 compressor with 9.0298 fJ of power delay product and minimum area occupation among the references. Based on real chip measurements, total die area occupation for proposed full adder and compressor is 0.505 µm2 and 1.092 µm2, respectively. Proposed circuits were applied to an 8-bit subtractor for orthopantomogram image processing to detect tooth core build up and restored with dental filling in order to maintain a crown restoration. Merits of proposed circuits both in IC design and image processing make these circuits suitable choice for bioelectronics chips. [ABSTRACT FROM AUTHOR]

• Using the carbon nanotube field-effect transistors technology to design approximate arithmetic circuits. • The gate diffusion input and dynamic threshold techniques are integrated to attain efficient circuits. • The presented approximate full adders show reliable performance during image processing. • The approximate full adders applied in bioimage processing. • Fat and water can be detected in bioimages by the presented approximate cells. Two new approximate full adders (FAs) are proposed by the multiplexers (MUXs) and OR gates with the gate diffusion input (GDI) technique. The cells are named GDI-based MUX approximate FAs (GMAFAs), GMAFA1, and GMAFA2. The threshold voltage drop of the GDI-based circuits is solved by carbon nanotube field-effect transistors (CNTFETs) technology and the dynamic threshold (DT) technique. The FAs have accurate C out , approximate Sum, and a low number of transistors. They are low-power, high-speed, and energy-efficient for ripple-carry adders (RCAs). The GMAFA1 and GMAFA2 have a total area of 0.068 µm2 and 0.119 µm2, respectively, which demonstrate 27.8% and 54.55% improvement in power-delay-area-product (PDAP) in comparison with the best references. The results of error distance (ED), normalized mean error distance (NMED), power signal-to-noise ratio (PSNR), and energy-saving confirm the accuracy of the presented cells for image processing applications. [Display omitted] [ABSTRACT FROM AUTHOR]

• Using the gate diffusion input technique in a new approximate full adder. • The full adder is implemented by carbon nanotube field-effect transistors. • The dynamic threshold technique improves the full adder swing. • A new approximate subtractor implemented by the full adder. • The approximate full adder and subtractor detect brain stroke. Approximate circuits are used in fault-tolerance applications, where carbon nanotube field-effect transistor (CNTFET) technology assists to achieve high performance. In this study, a new 8-transistor approximate full adder (FA) is designed and implemented using CNTFETs based on the gate diffusion input (GDI) technique. The FA is implemented in a ripple carry adder (RCA) and a 4-bit inexact subtractor for bioimages difference detection and finally stroke recognition. The non-full-swing outputs of the presented GDI cells are obviated by the dynamic threshold (DT) technique. The presented FA consumes a power of 2.0446 µW, while its power-delay-product (PDP) is 6.4536 fJ. Also, the superior results of peak signal-to-noise ratio (PSNR), power consumption, and PDP of the proposed subtractor are 30.866 dB, 9.642 µW, and 314.907 fJ, respectively. The FA has an area of 0.161 µm2 while the 4-bit subtractor occupies 2.18 µm2. The presented circuits show efficient performance for bioelectronics integrated circuits (ICs). [Display omitted] [ABSTRACT FROM AUTHOR]

Summary: Sophisticated systems take advantage of approximate circuits for energy management. A gate‐level structure is introduced to make a novel imprecise full adder (FA) cell by the gate diffusion input (GDI) strategy. The carbon nanotube field‐effect transistor (CNTFET) technology lowers the FA power, and the swing issue is resolved by the dynamic threshold (DT) technique. The FA specifications are 10 transistors, two internal nodes, 0.191‐μm2 area, three errors, and an error rate (ER) of 37.5%. Some inputs are directly passed to the final stage of the FA to reduce the delay and dynamic power. The FA is used in three 4:2 compressors with 12, 16, and 20 transistors, respectively. The compressors are based on the modified stacking concept to attain low power, small area, and high speed. The compressors are used up in the partial product reduction tree (PPRT) of a new 8‐bit inexact multiplier. Regarding the multiplier, the power–delay product (PDP) is decreased by 25.21%, and the normalized mean error distance (NMED) shows high accuracy. An imprecise discrete cosine transform (DCT) is implemented by the multiplier for image compression, and compared with the literature, the peak signal‐to‐noise ratio (PSNR) and structural similarity index metric (SSIM) are amended by 8.26% and 7.29%, respectively. [ABSTRACT FROM AUTHOR]

Integrated circuits (ICs) employ static and dynamic logic to improve performance and scalability. This paper presents a new circuit design approach named pseudo-dynamic logic (PDL), which shows the advantages of both static and dynamic cells. The PDL is evaluated by using a new full adder cell with 18 transistors. In the presented full adder, gate diffusion input (GDI), transmission gate (TG), and float techniques are combined, and pull-up or pull-down networks are changed into a new configuration so that the number of transistors and internal nodes will decrease. Post-layout simulations and digital image addition are performed to evaluate the real environment and practical application of the cell. Peak signal to noise ratio (PSNR), mean square error (MSE), and structural similarity index metric (SSIM) are calculated to study the cell performance in image processing. Compared to the dynamic and static circuits, the proposed PDL-based full adder cell performs better, and the results validate its effectiveness. [ABSTRACT FROM AUTHOR]

Here, a new 4:2 approximate compressor is presented by the gate diffusion input (GDI) technique. Although GDI cells suffer from threshold voltage drop, the dynamic threshold approach and carbon nanotube field‐effect transistors are merged to overcome the mentioned problem. The proposed cell has full‐swing outputs, while its error and power delay product are at low rates. Therefore, low voltage multipliers that are used in image processing can benefit from the proposed compressor. [ABSTRACT FROM AUTHOR]

Three new approximate subtractors are presented based on the gate diffusion input (GDI) technique which benefits from the dynamic threshold (DT) technique using carbon nanotube field-effect transistors (CNTFETs) technology. Proposed-1, Proposed-2, and Proposed-3 subtractors have 10, 8, and 6 transistors with a total area of 0.289 μm2, 0.123 μm2, and 0.065 μm2, respectively. In Proposed-1 and Proposed-2, only XOR and F1 gates are used, which respectively have 2 and 4 errors. To solve the non-full-swing defects of these two circuits, only three F2-GDI gates are used in the Proposed-3, which has 4 errors. The Proposed-1 gives 0.25 as error distance (ED) while two other circuits with a lower area have an ED of 0.5. The Proposed-3 has a simple, low-power, and ground-free structure. The subtractors are implemented in an 8 to 4 non-restoring divider in four different configurations including vertical, horizontal, square, and triangular. The drivers based on Proposed-2 and Proposed-3 are the best circuits with average power-delay-product (PDP) savings of 68.16% and 57.43%, respectively. Finally, the dividers are used in the change detection of medical images, where, the proposed circuits show better circuitry performance and image quality production. [ABSTRACT FROM AUTHOR]

Different digital multipliers have resulted from various algorithms and hardware designs. This article presents a high-performance multiplier by a novel AND gate and a modified hybrid full adder (FA) cell. The AND is designed by using the pass transistor logic (PTL) technique and a speed-up transistor, while the FA is based on the transmission gate (TG). Low-power, high-speed, low power-delay-product (PDP), and high competency of both circuits for using in sophisticated structures like multipliers are confirmed by mathematical relations. The proposed 4-bit array multiplier circuit along with the pad has a 2.87 mm2 total area and is investigated under different circumstances including V DD , frequency, load capacitances, and process-voltage-temperature (PVT) variations using Monte Carlo method (MCM) by HSPICE tool and 90 nm technology. The efficiency of the multiplier in image processing applications is proved with average improvements of 12.61% and 32.045% for peak signal-to-noise ratio (PSNR) and PDP compared to state-of-the-art designs, respectively. The overall results of the multiplier approve its capability for digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]