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A novel microprocessor-based platinum resistance temperature indicator has been developed and described. This indicator provides a linear performance over a wide dynamic temperature range of −183·0°C to +200°C with an accuracy of better than ±0·05°C. To easily carry out the linearization of platinum thermometer through software, the modified Callendar-Van Dusen equation is used. Test results are given to support the theory. [ABSTRACT FROM AUTHOR]

Multiplexers, as in the case of binary, are very useful building blocks in the development of quaternary systems. The use of quaternary multiplexer (QMUX) in the implementation of quaternary adder, subtractor and multiplier is described in this paper. Quaternary coded decimal (QCD) adder/subtractor and quaternary excess3 adder/subtractor realization using QMUX are also proposed. [ABSTRACT FROM AUTHOR]

A novel microprocessor-based temperature indicator has been developed and described. This indicator provides a linear performance over a wide dynamic temperature range of 0-100° C with an accuracy of ±0·1° C. The interfacing module reduces computing time required by the microprocessor for solving the thermistor equation. Test results are given to support the theory. [ABSTRACT FROM AUTHOR]

This paper proposes two circuits for the realization of analogue-to-quaternary converters (AQCs) viz., pipeline AQC and circulation AQC. The proposed AQCs make use of three quaternary circuits namely four level comparator, multiplexer and D flip-flops. These circuits and also the relevant control circuits required in the realization of AQCs are described. A comparison of the two methods is made. [ABSTRACT FROM AUTHOR]

Unary operators are functions of a single variable. Realization of quaternary unary operators (QUOs) using quaternary multiplexer (QMUX) is presented in this paper. QUOs are divided into eight groups on the basis of the number of change overs in the output for an input sequence of 0, 1, 2, 3. This grouping reduces the hardware required to realize them. QMUX with two, three, and four input lines are proposed for the realization of QUOs belonging to the eight groups. A systematic procedure for the selection of QMUX and the implementation of the QUOs are given. The QMUXs are designed using CMOS ICs. The hardware required for their implementation is also discussed. [ABSTRACT FROM AUTHOR]

This paper describes the implementation of the modified continuously variable slope delta modulator (MCVSD), in which the basic step size δ[sub 0] is made to vary as a function of input signal level. The information needed to carry out this is extracted at the local decoder output so that the coder and the decoder track each other. The result is a significant improvement in the dynamic range (about 15 dB) as compared to CVSD coder without degrading the peak signal to noise ratio. [ABSTRACT FROM AUTHOR]

A novel thermistor-based temperature indicator using an RC oscillator and an up/down counter has been developed and described. The indicator provides linear performance over a wide dynamic temperature range of 0-100°C. This indicator is free from the error due to lead resistances of the thermistor and gives a maximum error of ±0.1°C in the range O-100°C. Test results are given to support the theory. [ABSTRACT FROM AUTHOR]

Circuits for realizing serial quaternary-to-analogue converters (QACs) are proposed in this paper. Three techniques are presented based on Shannon-Rack decoder, sample/hold serial digital-to-analogue converter and cyclic digital-to-analogue converter. Circuits for the generation of control signals and the multiplexer required in the realization of the QACs are also described. A comparison of the three methods is made. [ABSTRACT FROM AUTHOR]

A quaternary multiplexer (QMUX) which uses CMOS integrated circuits is described. Circuit designs for 4-to-1 and 16-to-1 QMUX are considered. Three different circuits for the realization of a QMUX are proposed using QNAND gates, bilateral CMOS switches and analogue multiplexers. The three methods are compared. Applications of QMUXs in the development of circuits for addition, subtraction and multiplication of two quaternary digits (2-quits) and a 2-quit quaternary-to-analogue converter (QAC) are described. [ABSTRACT FROM AUTHOR]

This paper presents a new algorithm for the step-size change of instantaneous adaptive delta modulator. The present strategy is such that the step-size at any sampling instant can increase or decrease by either of the two constant factors or can remain the same, depending upon the combination of three or four most recent output bits. The quantizer has been simulated on a digital computer, and its performance compared with other quantizers. The figure of merit used is the SNR with gaussian signals as the input. The results indicate that the new design can give an improved SNR over a wider dynamic range and fast response to step inputs, as compared to the earlier systems. [ABSTRACT FROM AUTHOR]

The recent trend towards minimizing the interconnections in large scale integration (LSI) circuits has led to intensive investigation in the development of ternary circuits and the improvement of their design. The ternary multiplexer is a convenient and useful logic module which can be used as a basic building block in the design of a ternary system. This paper discusscs a systematic procedure for the simplification and realization of ternary functions using ternary multiplexers as building blocks. Both single level and multilevel multiplexing techniques are considered. The importance of the design procedure is highlighted by considering two specific applications, namely, the development of ternary adder/subtractor and TCD to ternary converter. [ABSTRACT FROM AUTHOR]

This paper describes the use of a ternary multiplexer as a building block in the implementation of ternary adders and subtractors and also in the development of ternary coded adders/subtractors. [ABSTRACT FROM AUTHOR]

The paper describes the application of the pipelining principle to the realization of an analogue-to-ternary converter. The circuit shows a considerable saving in hardware compared with an earlier proposed circuit. The main hardware components used are analogue comparators, subtractors and the delay elements; hence this method of A/T conversion can operate at a higher sampling frequency. [ABSTRACT FROM AUTHOR]

The multiplexer is one of the important building blocks in the design of binary digital system. The extension of this approach for a ternary system is considered in this article. The circuit realization of a three-line to one-line multiplexer with a ternary control input is examined. Three diffcrent circuits are proposed and a comparison made. The use of the multiplexer in ternary to analogue conversion and also in the reaization of a two-trit adder and subtractor are described. [ABSTRACT FROM AUTHOR]

Analogue and digital techniques for linearization of non-linear input-output relationship of transducers are briefly reviewed. The condition required for linearizing a non-linear function y=f(x) using a non-linear analogue-to-digital converter, is explained. A simple technique to construct a non-linear digital-to-analogue converter, based on ‘segments of equal digital interval’ is described. The technique was used to build an N-DAC which can be employed in a successive approximation or counter-ramp type ADC to linearize the non-linear transfer function of a thermistor-resistor combination. The possibility of achieving an order of magnitude higher accuracy in the measurement of temperature is shown. [ABSTRACT FROM AUTHOR]

A simple generalized technique for realizing a non-linear digital to analogue converter (N-DAC), based on the principle of ‘segments of equal digital interval” is described. The simplicity of the proposed technique is demonstrated by realizing an N-DAC having a square law transfer function. [ABSTRACT FROM AUTHOR]

A new digital polynomial generator using the principle of dual-slope analogue-todigital conversion is proposed. Techniques for realizing a wide range of integer as well as fractional coefficients to obtain the desired polynomial have been discussed. The suitability of realizing the proposed polynomial generator in integrated circuit form is also indicated. [ABSTRACT FROM AUTHOR]

An improved encoding scheme is proposed wherein the quantizer step size incorporates both instantaneous and syllabic adaptation. The information needed to carry out this adaptation is extracted at the coder after the D/A conversion of the digital output, so that the coder and the decoder track each other. A 5-bit coder has been designed and built which has a dynamic range of 38 dB with a constant SNR of 30 dB, and the quality of its output signal is found to be comparable to that of other coding schemes. [ABSTRACT FROM AUTHOR]

A new method of generating polynomials using microprocessors is proposed. The polynomial is generated as a 16-bit digital word. The algorithm for generating a variety of basic ‘ building block rsquo; functions and its implementation is discussed. A technique for generating a generalized polynomial based on the proposed algorithm is indicated. The performance of the proposed generator is evaluated using a commercially available microprocessor kit. [ABSTRACT FROM AUTHOR]

Constant current charging of a capacitor through a transistor gated by input pulses generates a linear staircase voltage across the capacitor. Discharging of the capacitor after the nth pulse by a voltage operated discharge switch makes the circuit a divide by n counter.
The two-diode storage counter described by Millman and Taub (1965) generates a non-linear staircase voltage. Consequently, linearization of staircase steps becomes essential for reliable operation of the circuit as a divide by n counter. This necessitates additional circuitry. The technique proposed here uses a single transistor and generates a linear staircase voltage across a capacitor by the constant current pulse charging technique described by the author (Shivaprasad 1970). A voltage operated discharge switch connected across the capacitor and arranged to discharge the capacitor after the nth step makes the circuit a divide by n counter. The circuit is particularly useful in counting of extremely low duty cycle pulses. [ABSTRACT FROM AUTHOR]

Examines the pulse-repetition frequency of a square waves. Synchronization between pulses and input square wave; Analysis of the output pulse width of the multivibrator; Components of the basic circuit arrangements.