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A multiplex, delay‐and‐sum (MDAS) architecture is proposed to implement a fixed‐focus receive beamformer such as the first stage of the synthetic aperture sequential beamforming (P‐SASB) and synthetic transmit beams combined with the P‐SASB (STB‐P‐SASB) beamforming methods. The output image of this architecture has a resolution and contrast‐to‐noise ratio (CNR) almost similar to that of the delay‐and‐sum (DAS) architecture. In the analog part of this architecture, there is no need to use any analog memory and in the digital part, the need to use high‐speed memories and interpolation filter is eliminated. In this architecture for each input channel, the power consumption in the mixed‐signal part is increased by approximately 1.14 mW in comparison to that of the DAS architecture. On the other hand, due to the elimination of the power consumption related to the interpolation filter in the digital part, the total power consumption of the MDAS architecture increases by a maximum of 9.2% compared to the DAS architecture. Also, the silicon area required to implement the mixed‐signal part of the MDAS architecture when implementing the first stage of P‐SASB and STB‐P‐SASB beamforming methods is reduced by about 3 times and increased by a maximum of 25%, respectively, compared to that of the DAS architecture. [ABSTRACT FROM AUTHOR]

Summary: In this article, a compact integrated high‐voltage (HV) pulser is presented, which can serve as an actuator in area‐limited medical ultrasound imaging applications. The proposed HV pulser is capable of producing bipolar return‐to‐zero (RTZ) HV pulses with a maximum peak‐to‐peak amplitude of 60 V. A novel RTZ stage including a new transistor gate–source protection scheme is used in this work, resulting in a reduced die area by enabling the use of an embedded transmit/receive (T/R) switch and obviating the need for a separate T/R switch. The proposed HV pulser also incorporates programmable delay elements by which the RTZ time can be controlled. By selecting the minimum allowed value of delay, the pulser is able to generate square‐wave HV pulses as well. Designed and implemented in a 0.18‐μm HV Bipolar‐CMOS‐DMOS (BCD) technology, the pulser occupies a layout area of 0.455 mm2. The function of the proposed design has been verified using post‐layout simulations when driving a 220‐pF capacitor in parallel with a 1‐kΩ resistor load. The simulation results indicate that the pulser consumes an average power of 14.85 mW when producing 2‐MHz, three‐cycle HV pulses with a pulse repetition frequency (PRF) of 5 kHz. [ABSTRACT FROM AUTHOR]

A new sample-and-hold (S&H) architecture is proposed for time-interleaved analog-to-digital converter (ADC). The use of this S&H circuit in front-end of a time-interleaved ADC system eliminates the need for sample-time calibration. Using the techniques of precharging and output capacitor coupling along with a new sampling technique called middle-plate-sampling can mitigate the stringent performance requirements for the opamp and sampling switches, resulting in low power consumption and allowing very high sampling rate. Simulated by HSPICE with a standard BSIM3v3 0.18 [micro]m technology, the S&H achieves 10-12 bits resolution for a 1.6-[V.sub.pp] output at 1-GHz sampling rate. The S&H dissipates 12 mW from a 1.8-V supply. Index Terms--Analog integrated circuits, analog-to-digital circuits (ADCs), CMOS analog integrated circuits, low power analog circuits, pipeline, sample-and-hold (S&H) circuits.

The second-order intercept point (IP2) performance of direct conversion receivers is limited by the second-order nonlinearity of the mixer. A new technique which is based on calibrating mixer by injecting a programmable nonlinear current into the mixer output is introduced in this paper. The proposed calibration technique can be used in multi-standard mixers. A CMOS mixer demonstrating the performance for Universal Mobile Telecommunication System application and working with supplies as low as 1 V is designed in a 65-nm technology. The simulation results show that the mixer IIP2 is improved more than 25 dB while the mixer current consumption is increased less than 1 mA. The calibration circuit is low noise not to affect the mixer noise figure. Index Terms--Calibration, CMOS, mixer, second-order input intercept point (IIP2), second-order intermodulation (IM2).

This brief presents a time-domain model for the slew rate of CMOS two-stage Miller compensated operational transconductance amplifiers. The effects of both the first- and second-stage currents are considered in this model and a simple analytical expression is given in terms of the compensation and load capacitors, output voltage change, and device sizes. HSPICE simulation results are provided to show the validity of the proposed model using a 0.25-[micro]m CMOS technology. Index Terms--Linear settling, operational transconductance amplifiers (OTAs), slew rate, switched-capacitor circuits.

This brief focuses on the comparative analysis of the parasitic sensitivity of different switched-capacitor summing-integrator structures employed in [SIGMA][DELTA] modulators. One summing-integrator structure with cross-coupled switches is found to be parasitic sensitive, whereas another summing-integrator structure without cross-coupled switches is found to be parasitic insensitive. The effect of the parasitic-sensitive and the parasitic-insensitive summing integrator on the performance of a second-order [SIGMA][DELTA] modulator is reported. Circuit simulations indicate a degradation of the signal-to-noise-plus-distortion ratio (SNDR) of the modulator from 89 dB to as !ow as 51 dB in the presence of certain parasitic capacitances when the parasitic sensitive summing integrator is used. This was found to be primarily due to a prominent second-harmonic component in the quantizer output. Whereas simulations using the parasitic-insensitive summing-integrator structure were found to cause no prominent harmonic distortion and, hence, no degradation of the SNDR in the presence of any parasitic capacitances. Index Terms--[SIGMA][DELTA] modulators, parasitic sensitivity, summing integrators, switched-capacitor circuits.

The CMOS scaling and power usage limitations make the calibration techniques inevitable in the design and implementation of pipeline analog-to-digital converters (ADCs) especially in high speed and high-resolution applications. In this brief, a new digital method is introduced which requires only a shift register and some logic blocks compared to traditional correlation-based background techniques meanwhile improving converter’s characteristics superior to prior methods. Here, two techniques are introduced to calibrate the linear and third-order non-linearities of the gain stages. Making use of the proposed algorithm, to the best of our knowledge, both the linear and non-linear errors in the multiplier digital-to-analog converter (MDAC) are estimated with lower number of conversion samples compared to the correlation-based reported methods. To verify and test the effectiveness of this new method, a model of 12-bit, 100 MS/s pipeline converter is calibrated through simulation. As a result, 21 dB and 25 dB improvements are achieved in behavioral simulated results of SNDR and SFDR respectively through about $1\cdot 8 \times 1 0^{6}$ conversion cycles and, INL and DNL of the ADC, are tuned to about +0.2/−0.3 LSB and +0.18/−0.11 LSB, respectively. [ABSTRACT FROM AUTHOR]

A prototype Gaussian minimum key shifting (GMSK) modulator for digital radio relay systems (DRRSs) standard without any external component has been designed and simulated in 1.4-GHz frequency band in a 0.6-/[micro]m CMOS process. The modulator including a compensation filter allows the digital frequency modulation at 1.6-Mb/s. Using a low-power frequency divider and a low-power low-phase noise oscillator, the power consumption of the modulator is minimized. Transistor and system level simulations demonstrate that the modulator meets the performance requirements of the DRRS standard. Circuit simulation with a 0.6-/[micro]m CMOS technology shows that the power consumption of the modulator is 37 mW from a 3 V power supply. Index Terms--Compensation technique, frequency synthesizers, Gaussian minimum phase shift keying, phase-locked loop (PLL), [SIGMA]-[DELTA] modulation.

The discrete-time [Delta][Sigma] modulator is transformed to the continuous-time [Delta][Sigma] modulator. For either nonreturn to-zero or return to-zero feedback, the loop transfer functions of the continuous-time and discrete-time modulators can be made exactly equivalent. Hence, a stable discrete-time [Delta][Sigma] modulator is mapped to a stable continuous-time [Delta][Sigma] modulator having the same SNR. The anti-alias (image rejection) properties of the continuous-time modulator are described. Experimental results for a tunable 40 MHz-70 MHz continuous-time Gm-C modulator are shown to verify the theory. A master-slave tuning scheme is developed to tune the Gm-C [Delta][Sigma] loop filter. Index Terms - Analog-to-digital converter, bandpass [Delta][Sigma] ADC's, continous-time filtering, converter, [Delta][Sigma] modulator.