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We characterized resistance drift in phase change memory devices in the 80 K to 300 K temperature range by performing measurements on 20 nm thick, ~70-100 nm wide lateral Ge2Sb2Te5 (GST) line cells. The cells were amorphized using 1.5-2.5 V pulses with ~50-100 ns duration leading to ~0.4-1.1 mA peak reset currents resulting in amorphized lengths between ~50 and 700 nm. Resistance drift coefficients in the amorphized cells are calculated using constant voltage measurements starting as fast as within a second after amorphization and for 1 hour duration. Drift coefficients are in the range between ~0.02 and 0.1 with significant device-to-device variability and variations during the measurement period. At lower temperatures (higher resistance states) some devices show a complex dynamic behavior, with the resistance repeatedly increasing and decreasing significantly over periods in the order of seconds.

Narrow-channel accumulated body nMOSFET devices with p-type side-gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (Vside). The subthreshold slope (SS) and drain induced barrier lowering (DIBL) decrease and threshold voltage (Vt) increases linearly with reduced temperature and reduced side-gate bias. Detailed analysis on a 27 nm x 78 nm (width x length) device show SS decreasing from 115 mV/dec at 400 K to 90 mV/dec at 300 K and down to 36 mV/dec at 100 K, DIBL decreasing by approximately 10 mV/V for each 100 K reduction in operating temperature, and Vt increasing from 0.42 V to 0.61 V as the temperature is reduced from 400 K to 100 K. Vt can be adjusted from ~ 0.3 V to ~ 1.1 V with ~0.3 V/V sensitivity by depletion or accumulation of the body of the device using Vside. This high level of tunability allows electronic control of Vt and drive current for variable temperature operation in a wide temperature range with extremely low leakage currents (< 10-13 A)., Comment: 6 pages, 8 figures, Submitted to IEEE T-ED

We have computationally demonstrated logic function implementations using lateral and vertical multi-contact phase change devices integrated with CMOS circuitry, which use thermal cross-talk as a coupling mechanism to implement logic functions at smaller CMOS footprints. Thermal-crosstalk during the write operations is utilized to recrystallize the previously amorphized regions to achieve toggle operations. Amorphized regions formed between different pairs of write contacts are utilized to isolate read contacts. Typical expected reduction in CMOS footprint is ~ 50% using the described approach for toggle-multiplexing, JK-multiplexing and 2x2 routing. The switching speeds of the phase change devices are in the order of nanoseconds and are inherently non-volatile. An electro-thermal modeling framework with dynamic materials models are used to capture the device dynamics, and current and voltage requirements., Comment: 7 pages, 6 figures

Scaling of two dimensional six-contact phase change devices that can perform toggle logic operations is analyzed through 2D electrothermal simulations with dynamic materials modeling, integrated with CMOS access circuitry. Toggle configurations are achieved through a combination of isolation of some contacts from others using amorphous regions and coupling between different regions via thermal crosstalk. Use of thermal crosstalk as a coupling mechanism in a multi-contact device in the memory layer allows implementation of analog routing and digital logic operations at a significantly lower transistor count, with the added benefit of non-volatility. Simulation results show approximately linear improvement in peak current and voltage requirements with thickness scaling.

We observed resistance drift in 125 K - 300 K temperature range in melt quenched amorphous Ge2Sb2Te5 line-cells with length x width x thickness = ~500 nm x ~100 nm x ~ 50 nm. Drift coefficients measured using small voltage sweeps appear to decrease from 0.12 +/- 0.029 at 300 K to 0.075 +/- 0.006 at 125 K. The current-voltage characteristics of the amorphized cells measured in the 85 K - 300 K using high-voltage sweeps (0 to ~25 V) show a combination of a linear, low-field exponential and high-field exponential conduction mechanisms, all of which are strong functions of temperature. The very first high-voltage sweep after amorphization (with electric fields up to ~70% of the breakdown field) shows clear hysteresis in the current-voltage characteristics due to accelerated drift, while the consecutive sweeps show stable characteristics. Stabilization was achieved with 50 nA compliance current (current densities ~104 A/cm^2), preventing appreciable self-heating in the cells. The observed acceleration and stoppage of the resistance drift with the application of high electric fields is attributed to changes in the electrostatic potential profile within amorphous Ge2Sb2Te5 due to trapped charges, reducing tunneling current. Stable current-voltage characteristics are used to extract carrier activation energies for the conduction mechanisms in 85 K - 300 K temperature range. The carrier activation energy associated with linear current-voltage response is extracted to be 331 +/- 5 meV in 200 - 300 K range, while carrier activation energies of 233 +/- 2 meV and 109 +/- 5 meV are extracted in 85 K to 300 K range for the mechanisms that give exponential current-voltage responses.

Germanium antimony telluride has been the most used and studied phase-change material for electronic memory due to its suitable crystallization temperature, amorphous to crystalline resistance contrast, and stability of the amorphous phase. In this work, the segregation of Ge in a Ge2Sb2Te5 film of 30 nm thickness during heating inside the transmission electron microscope was observed and characterized. The Ge2Sb2Te5 film was deposited using sputtering on a Protochips Fusion holder and left uncapped in atmosphere for about four months. Oxygen incorporated within the film played a significant role in the chemical segregation observed which resulted in amorphous Ge-O grain boundaries and Sb and Te rich crystalline domains. Such composition changes can occur when the phase-change material interfaces insulating oxide layers in an integrated device and would significantly impact its electrical and thermal properties., Comment: 12 pages, 6 figures

Resistance drift in phase change materials is characterized in amorphous phase change memory line-cells from 300 K to 125 K range and is observed to follow the previously reported power-law behavior with drift coefficients in the 0.07 to 0.11 range in dark. While these drift coefficients measured in dark are similar to commonly observed drift coefficients (~0.1) at and above room temperature, measurements under light show a significantly lower drift coefficient (0.05 under illumination versus 0.09 in dark at 150K). Periodic on/off switching of light shows sudden decrease/increase of resistance, attributed to photo-excited carriers, followed by a very slow response (~30 minutes at 150 K) attributed to contribution of charge traps. Continuation of the resistance drift at low temperatures and the observed photo-response suggest that resistance drift in amorphous phase change materials is predominantly an electronic process., Comment: Added relevant references. Corrected typing and formatting errors

We model electrical conductivity in metastable amorphous $Ge_{2}Sb_{2}Te_{5}$ using independent contributions from temperature and electric field to simulate phase change memory devices and Ovonic threshold switches. 3D, 2D-rotational, and 2D finite element simulations of pillar cells capture threshold switching and show filamentary conduction in the on-state. The model can be tuned to capture switching fields from ~5 to 40 MV/m at room temperature using the temperature dependent electrical conductivity measured for metastable amorphous GST; lower and higher fields are obtainable using different temperature dependent electrical conductivities. We use a 2D fixed out-of-plane-depth simulation to simulate an Ovonic threshold switch in series with a $Ge_{2}Sb_{2}Te_{5}$ phase change memory cell to emulate a crossbar memory element. The simulation reproduces the pre-switching current and voltage characteristics found experimentally for the switch + memory cell, isolated switch, and isolated memory cell.

Phase change memory (PCM) is an emerging high speed, high density, high endurance, and scalable non-volatile memory technology which utilizes the large resistivity contrast between the amorphous and crystalline phases of chalcogenide materials such as Ge2Sb2Te5 (GST). In addition to being used as a standalone memory, there has been a growing interest in integration of PCM devices on top of the CMOS layer for computation in memory and neuromorphic computing. The large CMOS overhead for memory controllers is a limiting factor for this purpose. Transferring functionality like routing, multiplexing, and logic to the memory layer can substantially reduce the CMOS overhead, making it possible to integrate 100s of GB of PCM storage on top of a conventional CPU. In this work, we present computational analysis of a phase change device concept that can perform toggle operations. The toggle functionality is achieved using two physical mechanisms: (i) isolation of different read contacts due to amorphization between different write contact pairs, and (ii) thermal cross-talk between a molten region and a previously amorphized region. Phase-change devices with six contacts can be implemented as toggle flip-flops, multiplexer, or demultiplexer when interfaced with CMOS transistors. Here, we demonstrate the operation of the device as a toggle flip-flop with 5 transistors, requiring ~50% of the footprint compared to conventional CMOS alternatives, with the added advantage of non-volatility.

We present thermodynamic crystallization and melting models and calculate phase change velocities in $Ge_2 Sb_2 Te_5$ based on kinetic and thermodynamic parameters. The calculated phase change velocities are strong functions of grain size, with smaller grains beginning to melt at lower temperatures. Phase change velocities are continuous functions of temperature which determine crystallization and melting rates. Hence, set and reset times as well as power and peak current requirements for switching are strong functions of grain size. Grain boundary amorphization can lead to a sufficient increase in cell resistance for small-grain phase change materials even if the whole active region does not completely amorphize. Isolated grains left in the amorphous regions, the quenched-in nuclei, facilitate templated crystal growth and significantly reduce set times for phase change memory cells. We demonstrate the significance of heterogeneous melting through 2-D electrothermal simulations coupled with a dynamic materials phase change model. Our results show reset and set times on the order of ~1 ns for 30 nm wide confined nanocrystalline (7.5 nm - 25 nm radius crystals) phase change memory cells.