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Active gate driving of power devices seeks to shape switching trajectories via the gate, for example, to reduce EMI without degrading efficiency. To this end, driver ICs with integrated arbitrary waveform generators have been used to achieve complex gate signals. This article describes, for the first time, the implementation details of a digitally programmable arbitrary waveform gate driver capable of a 10-GHz waypoint rate, including comprehensive design considerations for critical high-speed subsystems that codify the tradeoff in flexibility, speed, and area. The design, which is taped out in a 180-nm high-voltage CMOS process, utilizes buffers that switch up to ten times in a single clock cycle to overcome the limited achievable clock speed of high-voltage silicon integrated circuits and a fully digital architecture to provide robustness under high slew rates of the ground rail. The driver IC has networks of 100-ps delay elements that are configured prior to a switching transient, to selectively control an array of fast, parallel-connected drivers with different output impedances. Key to the high timing resolution are high-speed asynchronous circuits for memory readout, output buffering, and pulse generation. The driver IC is experimentally evaluated to have a 100-ps resolution and to operate reliably in a 400-V gallium nitride (GaN) bridge leg, under ground-rail voltage slew rates peaking at over 100 V/ns. Design rules are provided to obtain an architecture with the least area for a given set of timing and impedance resolution requirements. The reported design methods enable complex driving waveforms to be applied during nanosecond-scale transients of GaN power devices and demonstrate how digitally programmable active gate drivers for GaN power FETs can be designed to meet a given set of application requirements.

Active gate driving has been demonstrated to beneficially shape switching waveforms in Si- and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limited to altering a single drive parameter once per switching event, either during or outside of the transient. This paper demonstrates a gate driver with a timing resolution and range of output resistance levels that surpass those of existing gate drivers or arbitrary waveform generators. It is shown to permit active gate driving with a bandwidth that is high enough to shape a GaN switching during the transient. The programmable gate driver has integrated high-speed memory, control logic, and multiple parallel output stages. During switching transients, the gate driver can activate a near-arbitrary sequence of pull-up or pull-down output resistances between 0.12 and 64 Ω. A hybrid of clocked and asynchronous control logic with 150-ps delay elements achieves an effective resistance update rate of 6.7 GHz during switching events. This active gate driver is evaluated in a 1-MHz bridge-leg converter using EPC2015 GaN FETs. The results show that aggressive manipulation of the gate-drive resistance at sub-nanosecond resolutions can profile gate waveforms of the GaN FET, thereby beneficially shaping the switch-node voltage waveform in the power circuit. Examples of open-loop active gate driving are demonstrated that maintain the low switching loss of constant-strength gate driving, while reducing overshoot, oscillation, and EMI-generating high-frequency spectral content.

Capitalising on the high-speed switching capability of 650 V GaN FETs in power-electronic bridge-legs is challenging. Whilst active gate driving has previously been shown to help overcome adverse switching behaviour, the best results are likely to be achieved through a combination of uncompromised circuit layout and active gate driving. A fully integrated dual-channel driver would minimise external circuitry and allow power devices to be placed as close together as possible. This would facilitate simultaneous minimization of parasitic inductances in the gate-drive and power-circuit loops. Other benefits would include ease of use, lower BOM cost, and providing a step towards full integration of driver and power stage. This paper presents three circuit blocks vital to the implementation of a fully integrated dual-channel gate driver – A 100 ps resolution, digitally-controlled active gate driver IC, a sub-ns propagation delay level shifter with 200 V/ns slew-rate immunity, and a regulated bootstrap supply that maintains its output voltage regardless of any switch-node undershoot during switching events. Measurement results show the efficacy of the high-resolution active gate driver in a GaN bridge leg, and the sub-ns propagation delay of the level shifter, both fabricated in a 50 V CMOS process. Simulation results demonstrate the slew-immunity of the level shifter, and operation of the bootstrap supply. It is also inferred how to increase the voltage rating of the level-shifter and bootstrap without adversely affecting performance.

Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and sub-ns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/( $\mu $ mV), which is an $1.7\times $ improvement on the next best reported level shifter for this type of application.

Active gate driving provides an opportunity to reduce EMI in power electronic circuits. Whilst it has been demonstrated for MOS-gated silicon power semiconductor devices, reported advanced gate driving in wide-bandgap devices has been limited to a single impedance change during the device switching transitions. For the first time, this paper shows multi-point gate signal profiling at the sub-ns resolution required for GaN devices. A high-speed, programmable active gate driver is implemented with an integrated high-speed memory and output stage to realise arbitrary gate pull-up and pulldown resistance profiles. The nominal resistance range is 120 μΩ to 64 Ω, and the timing resolution of impedance changes is 150 ps. This driver is used in a 1 MHz GaN bridge leg that represents a synchronous buck converter. It is demonstrated that the gate voltage profile can be manipulated aggressively in nanosecond scale. It is observed that by profiling the first 5 ns of the control device's gate voltage transient, a reduction in switch-node voltage oscillations is observed, resulting in an 8–16 dB reduction in spectral power between 400 MHz and 1.8 GHz. This occurs without an increase in switching loss. A small increase in spectral power is seen below 320 MHz. As a baseline for comparison, the GaN bridge leg is operated with a fixed gate drive strength. It is concluded that p-type gate GaN HFETs are actively controllable, and that EMI can be reduced without increasing switching loss.

The application of active gate driving to 40 V GaN FETs has previously been shown to reduce ringing and EMI-generating spectral content in the switch-node voltage waveforms. This paper, for the first time, shows active gate driving applied to 650 V GaN FETs, and the shaping of device voltages and currents during switching transients. A custom integrated active gate driver is used, which can dynamically vary its output resistance from 0.12 to 64 Ω, with a 150 ps timing resolution. At 200 V DC link and 10 A load current, a significant degree of control over the active-switch drain current and switch-node voltage is demonstrated, for both buck and boost mode operation. The current overshoot and ringing in the power waveforms due to circuit parasitics are actively reduced and the voltage oscillations in the DC link are damped. The timing of resistance sequences is shown to be critical to the success of active shaping methods, thus justifying the unparalleled 150 ps resolution of the driver. Under continuous operation and at reduced ratings of 100 V and 2 A load current the significant control of the switch node voltage and voltage spectra is also demonstrated. The switching delay is reduced, and parts of the spectrum are reduced by up to 9 dB, equivalent to the effect of tripling the gate resistance but without any reduction in the overall switching speed.

Energy harvesting is showing great promise for powering wireless sensors. However, under intermittent environmental power, low-power harvesting systems designed for stable conditions suffer reduced effectiveness or fail entirely. This work aims to improve a harvester's capability to extract useful power from low and intermittent vibration sources, by addressing the power-conditioning interface circuitry between the harvester and load. In view of this, two specific challenges are analyzed. The first challenge is that of start-up, where the goal is to make as short as possible the transition from completely depleted energy storage to the first powering-up of a load. The second challenge is to improve the energy transmission to a load after its first powering-up, under intermittent excitation. The investigation uses an ultra-low-power and fully-autonomous kinetic energy harvesting system under intermittent excitation. A number of solutions are presented. Decoupling filters between parallel converters and the harvester are used to demonstrate the importance of maintaining the optimal harvester loading, even during short transients. Input-power-dependent power gating of the power conditioning is also demonstrated. Both methods demonstrated experimentally using discrete circuit implementations, and shown to successfully increase the start-up speed and operational frequency of the load. The achieved reduction in start-up time is ~ 67% at a maximum harvestable power of 135 μW, under a predefined profile of pulsed excitation at 3 m·s -2 . The experimental results provide insight into complex transient interactions of the harvester and power conditioning.

This paper presents a novel routing algorithm called eXtended Torus routing algorithm for networks-on-chip (XTRANC) which supports topologyies based on a variable number and size of inner-torus building blocks. The inner-tori partition a traditional mesh network into an arbitrary number of sub-networks to increase the mesh performance. The sub-networks can generate non-regular global topologies which are also supported by the XTRANC algorithm. XTRANC is especially suitable for dynamically reconfigurable networks mapped to commercial FPGAs in which additional links are added to the mesh topology at run-time to reduce congestion depending on application behaviour and resource availability. XTRANC allows the insertion of links as requested by different parts of the application without centralized control and this research shows that despite this dynamic behaviour the routing algorithm remains deadlock free.

To solve the grand challenges in contemporary chip design, such as process-to-core mapping, energy reduction, and maintenance of programmer/hardware abstraction, we advocate for self-optimizing (emergent) networks-on-chip (NoC). In these networks, topology and information flow adapt dynamically to maximize the network throughput or minimize the network latency via distributed application of microrules. In this paper, we introduce the concept of emergent small-world NoCs and discuss novel design decisions, e.g., Skip-links, that improve performance and reduce energy consumption of multicore systems. More precisely, we demonstrate that our proposed solution is able to adapt to a wide range of traffic patterns and provide reductions in data hop count of up to 20 percent while maintaining energy and area costs. We show how emergent networks can be useful for on-chip processor-to-processor communications, and also demonstrate how SoC and off-chip I/O traffic may be optimized for latency and critical load.

A new design method for producing high-performance and power-rail slew-tolerant floating-voltage level shifters is presented, offering increased speed, reduced power consumption, and smaller layout area compared with previous designs. The method uses an energy-saving pulse-triggered input, a high-bandwidth current mirror, and a simple full latch composed of two inverters. A number of optimizations are explored in detail, resulting in a presented design with a dVdd/dt slew immunity of 30 V/ns, and near-zero static power dissipation in a 180-nm technology. Experimental results show a delay of below 370 ps for a level-shift range of 8-20 V. Postlayout simulation puts the energy consumption at 2.6 pJ/bit at 4 V and 7.2 pJ/bit at 20 V, with near symmetric rise and fall delays.

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.

We address routing in Networks-On-Chip (NoC) architectures that use irregular mesh topologies with Long-Range Links (LRL). These topologies create difficult conditions for routing algorithms, as standard algorithms assume a static, regular link structure and exploit the uniformity of regular meshes to avoid deadlock and maintain routability. We present a novel routing algorithm that can cope with these irregular topologies and adapt to run-time LRL insertion and topology reconfiguration. Our approach to accommodate dynamic topology reconfiguration is to use a new technique that decomposes routing relations into two stages: the calculation of output ports on the current minimal path and the application of routing restrictions designed to prevent deadlock. In addition, we present a selection function that uses local topology data to adaptively select optimal paths. The routing algorithm is shown to be deadlock-free, after which an analysis of all possible routing decisions in the region of an LRL is carried out. We show that the routing algorithm minimises the cost of sub-optimally placed LRL and display the hop savings available. When applied to LRLs of less than seven hops, the overall traffic hop count and associated routing energy cost is reduced. In a simulated 8x8 network the total input buffer usage across the network was reduced by 6.5%.

In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultralow-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic ‘one’ is achieved, which is problematic in an SE-SRAM cell with a 36% improvement compared to standard 6T SRAMs. A 16 × 16 × 32 bit SRAM with proposed and standard 6T bitcells is simulated and evaluated for read SNM, write-ability and power. The dynamic and leakage power dissipation in the proposed 6T SRAM are reduced by 28% and 21%, respectively, as compared to standard 6T SRAM.

Deeply embedded systems often have the tightest constraints on energy consumption, requiring that they consume tiny amounts of current and run on batteries for years. However, they typically execute code directly from flash, instead of the more energy efficient RAM. We implement a novel compiler optimization that exploits the relative efficiency of RAM by statically moving carefully selected basic blocks from flash to RAM. Our technique uses integer linear programming, with an energy cost model to select a good set of basic blocks to place into RAM, without impacting stack or data storage. We evaluate our optimization on a common ARM microcontroller and succeed in reducing the average power consumption by up to 41% and reducing energy consumption by up to 22%, while increasing execution time. A case study is presented, where an application executes code then sleeps for a period of time. For this example we show that our optimization could allow the application to run on battery for up to 32% longer. We also show that for this scenario the total application energy can be reduced, even if the optimization increases the execution time of the code.

This paper presents an analysis of the energy consumption of an extensive number of the optimisations a modern compiler can perform. Using GCC as a test case, we evaluate a set of ten carefully selected benchmarks for five different embedded platforms. A fractional factorial design is used to systematically explore the large optimisation space (2^82 possible combinations), whilst still accurately determining the effects of optimisations and optimisation combinations. Hardware power measurements on each platform are taken to ensure all architectural effects on the energy consumption are captured. We show that fractional factorial design can find more optimal combinations than relying on built in compiler settings. We explore the relationship between run-time and energy consumption, and identify scenarios where they are and are not correlated. A further conclusion of this study is the structure of the benchmark has a larger effect than the hardware architecture on whether the optimisation will be effective, and that no single optimisation is universally beneficial for execution time or energy consumption., 14 pages, 7 figures

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.

In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our selfoptimising NoC topology: Skip-links, which inserts long-range links into a standard mesh. We evaluate the performance of Skip-links at run-time against the optimal configuration, as determined by static analysis, for both the transpose and tornado traffic patterns. We show that the local decision-making algorithm employed by Skip-links comes close to optimum, carrying 70% of theoretical maximum traffic flows for tornado traffic, and reducing average hop counts by 18% for transpose traffic.

This thesis describes the development of an on-chip point-to-point link, with particular emphasis on the reduction of its global metal area footprint. To reduce its metal footprint, the interconnect uses a serial transmission approach. 8-bit data is sent using just two wires, through a pulse-based technique, inspired by the GasP interconnect from Sun Microsystems. Data and control signals are transmitted bi-directionally on a wire using this double-edged, pulse-based signalling protocol, and formatted using a variant of dual-rail encoding. These choices enable a reduction in the number of wires needed, an improvement in the acknowledgement overhead of the asynchronous protocol, and the ability to cross clock domains without synchronisation hazards. New, stateful, repeaters are demonstrated, and results from spice simulations of the system show that data can be transferred at over 1Gbit/s, over 1mm of minimum-sized, minimally-spaced metal 5 wiring, on a 180nm (0.18um) technology. This reduces to only 926Mbit/s, when 10mm of wiring is considered, and represents a channel utilisation of a very attractive 45% of theoretical capacity at this length. Analysis of latencies, energy consumption, and area use are also provided. The point-to-point link is then expanded with the invention and demonstration of a router and an arbitrated merge element, to produce a Network-on-Chip (NoC) design, called RasP. The full system is then evaluated, and peak throughput is shown to be 763Mbit/s for 1mm of wiring, reducing to 599Mbit/s for 10mm of the narrow metal 5 interconnect. Finally, RasP is compared in performance with the Chain interconnect from the University of Manchester. Results for the metrics of throughput, latency, energy consumption and area footprint show that the two systems perform very similarly — the maximum absolute deviation is under 25% for throughput, latency and area; and the energy-efficiency of RasP is approximately twice that of Chain. Between the two systems, RasP has the smaller latency, energy and area requirements and is shown to be a viable alternative NoC design.

We present RasP, our asynchronous on-chip-network, which uses high-speed pulse-based signalling techniques. RasP offers numerous advantages over conventional interconnects, such as clock-domain crossing and skew tolerance. Most importantly, it features a very small global-wiring footprint. This compact nature allows a system designer to give priority to link bandwidth or signal-to-noise ratios, rather than being restricted by lane areas. We describe our point-to-point link and develop it into a fully-routable system, with a repeater, router, arbiter and multiplexer. Simulations give throughput figures of between 1Gbit/s and 700Mbit/s in a 0.18mum technology, depending on interconnect length. We also show that it compares favourably in performance and area to Bainbridge et al.'s Chain interconnect.

This paper demonstrates the use of passive voltage multipliers for rapid start-up of sub-milliwatt electromagnetic energy harvesting systems. The work describes circuit optimization to make as short as possible the transition from completely depleted energy storage to the first powering-up of an actively controlled switched-mode converter. The dependency of the start-up time on component parameters and topologies is derived by simulation and experimentation. The resulting optimized multiplier design reduces the start-up time from several minutes to 1 second. An additional improvement uses the inherent cascade structure of the voltage multiplier to power sub-systems at different voltages. This multi-rail start-up is shown to reduce the circuit losses of the active converter by 72% with respect to the optimized single-rail system. The experimental results provide insight into the multiplier's transient behaviour, including circuit interactions, in a complete harvesting system, and offer important information to optimize voltage multipliers for rapid start-up.