Search

It is commonly thought that, in the development of SiC power devices with low on-state resistance (Ron), several critical processes in the device fabrication line can strongly impact the final warpage of wafers. High warpage would lead to bad definition of masks, preventing uniform deposition of resist materials and disturbing the normal handling procedures. All these factors would then result in a potential decrease of the electrical yield of the devices, especially for MOSFETs. This study reveals the lack of correlation between critical line processes such as epitaxial growth, oxidations, ion implantations, annealing processes with the final bending of wafers. Conversely, a strong dependence with the resistivity of the substrates is observed. A new parameter defined as RMR (Resistivity Modulation Rate) is taken proposed and, together with the starting value of ingot resistivity, this parameter shows a strong relationship with the final warpage after wafer thinning. A safe region having warpage low enough to allow the workability of the wafers is found.

In this work many steps concerning the epitaxial layer growth on 4H-SiC are studied, evaluated and optimized to obtain high quality 4H-SiC epitaxy. The processes evaluated have been studied on a Hot Wall CVD reactor. The first step related to the substrate surface etching has been tuned by choosing the H2 flow, temperature and process time at which most of defects (mainly stacking faults) are not propagated. Then, the buffer layer step has been optimized by increasing the thickness at which an effective reduction of defect density and an improved electrical performance of power devices have been detected. Also, during the buffer layer growth a strong dependence between basal plane dislocations propagation and the growth rate has been observed. A crucial step carefully studied has been the drift layer growth. It was optimized by increasing the growth rate (13

In this work a deep investigation of the dislocation on 4H-SiC substrate has been shown. The dislocation intersecting the surface were enhanced by KOH etching at 500 deg. C. performed on whole 6 inches substrate. A comparison between basal plane dislocations and threading screw dislocations in the substrate with the defects in the epitaxial layer (mainly stacking faults and carrots) was performed. The comparison between shows a correlation between basal plane dislocations density and stacking faults density maps.

In this work the deposition of buffer layer has been studied in order to increase the quality of the epitaxial layer and improve the performance of device. The comparison between two different thicknesses of buffer layer reveals a decrease of crystallographic defects and an improvement of electrical parameters of MOSFET device as leakage current and breakdown voltage.

Si l icon car b ide (Si C ) man u f act u ring is transitioning from 4 inch wafers to 6 inch wafers for production line devices. The main obstacle for SiC manufacturing high yield is defect control. Defectiveness inline control is well established for silicon power device. However, there are two main challenges related to SiC technology. The first challenge is incoming 4H-SiC substrates defectivity and epi layer crystallographic defects. The second challenge is inline defect detection at process steps such as implantation and annealing activation [,]. Defect detection and classification are difficult with current defect inspection tools because of substrate transparency at visible light, color variation, roughness, and wafers’ high warpage. In addition, SiC device integration has been requesting specific optimization. In this paper, collaboration studies have been done to develop solutions to these challenges. Yield correlation analyses have validated the process control flow set to address these two major challenges and to enable the fast ramp of the 6” production line of SiC devices.

We present a temperature-dependence electrical characterization of the oxide/semiconductor interface in MOS capacitors with a SiO2layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The post deposition annealing process in N2O allowed to achieve an interface state density Dit 9.0×1011cm-2eV-1below the conduction band edge. At room temperature, an electron barrier height (conduction band offset) of 2.8 eV was measured using the standard Fowler-Nordheim tunneling model. The electron conduction through the SiO2insulating layer was evaluated by studying the experimental temperature dependence of the gate current. In particular, the Fowler-Nordheim electron barrier height showed a negative temperature coefficient (dφB/dT= - 0.98 meV/°C), which is very close to the expected value for an ideal SiO2/4H-SiC system. This result, obtained for deposited SiO2layers, is an improvement compared to the values of the temperature coefficient of the Fowler-Nordheim electron barrier height reported for thermally grown SiO2. In fact, the smaller dependence ofφBon the temperature observed in this work represents a clear advantage of our deposited SiO2for the operation of MOSFET devices at high temperatures.

This work reports on the physical and electrical characterization of the oxide/semiconductor interface in MOS capacitors with the SiO2 layer deposited by a high temperature process from dichlorosilane and nitrogen-based vapor precursors and subjected to a post deposition annealing process in N2O. Low interface state density (Dit ≈ 9.0×1011cm-2eV-1) was found at 0.2 eV from EC, which is comparable to the values typically obtained in other lower temperature deposited oxides (e.g., TEOS). A barrier height of 2.8 eV was derived from the Fowler-Nordheim plot, very close to the ideal value expected for SiO2/4H-SiC interface. Basing on these preliminary results, the integration in MOSFETs devices can be envisaged.

The surface preparation of 4H-SiC substrate plays a crucial role for the epitaxial growth. In the present work, the Hydrogen etching influence on 4H-SiC surface of substrate before the growth process was studied. The epi-layer was grown with a commercial low-pressure, hot-wall Chemical Vapor Deposition (CVD) reactor by Tokyo Electron Limited. The etching time of the surface was increased until three time (x3) respect with the value (x1) usually adopted for the growth. Photoluminescence and optical inspection analyses show a clear relationship between the etching time and the defectivity (stacking faults, carrots, comets, triangles and pits). Atomic Force Microscope (AFM) measurements also show an increase of step bunching with the etching time.

4H-SiC defects evolution after thermal processes has been evaluated. Different annealing temperatures have been used to decrease the defect density of epitaxial layer (as stacking faults) and recover the damage occurred after ion implantation. The propagation of defects has been detected by Photoluminescence tool and monitored during the thermal processes. The results show that implants do not affect the surface roughness and how a preliminary annealing process, before ion implantation step, can be useful in order to reduce the SFs density. It shown the effect of tuned thermal process. A kind of defect, generated by implant and subsequent annealing, can be removed by an appropriate thermal budget, while others can increase. A fine tuning of thermal process parameters, temperature and timing, is useful to recover the crystallographic quality of the epilayer and increase the yield of the power device.

In this paper the defects generated by ion implantation in 4H-SiC DIMOSFET (Double Implanted MOSFETs), and their evolution after annealing process, have been studied in detail. The point defects generated by the source or body implantation process have been detected by micro-photoluminescence (µPL) and the effect of these defects on the electrical characteristics of the DIMOSFET has been studied. The role of the annealing process has been carefully investigated by using different temperatures. It appears fundamental for the restoring of the crystal damage. The effect of the ion implantation dose has been investigated as well. By reducing the source ion implanted dose a large decrease of point defects has been detected and a considerable improvement of the electrical characteristic of the DIMOSFET has been observed.

In this paper the influence of point defects generated by the ion implantation process in 4H-SiC DIMOSFET has been studied in detail. The point defects generated by the source or body implantation process have been detected by micro-photoluminescence and the effect of these defects on the electrical characteristics of the DIMOSFET has been studied. In particular it has been observed that a reduction of the source ion implanted dose produces a large reduction of point defects in the source region and a considerable improvement of the electrical characteristic of the DIMOSFET.

Thermal annealing plays a crucial role for healing the defectiveness in the ion implanted regions of DIMOSFETs (Double Implanted MOSFETs) devices. In this work, we have studied the effect of a double step annealing on the body (Al implanted) and the source (P implanted) regions of such devices. We found that a high temperature annealing (1750°C, 1h) followed by a lower temperature one (1500°C, 4h) is mandatory to achieve low defects concentration and good crystal quality in both the n-and p-type zones of the device.

In this paper a comparative study of the impact of N2O and POCl3 annealing on the SiO2/SiC system is presented, combining nanoscale electrical characterization of SiC surface doping by scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM) to the conventional capacitance-voltage (C-V) and current-voltage (I-V) measurements on MOS-based devices. A significant reduction of the interface states density (from 1.8×1012 to 5.7×1011 cm-2eV-1) and, correspondingly, an increase in the carrier mobility (from 19 to 108 cm2V-1s-1) was found moving from N2O to POCl3 annealing. Furthermore, SSRM measurements on bare p+-type SiC regions selectively exposed to N2O and POCl3 at high temperature provided the direct demonstration of the incorporation of N or P-related donors in the SiC surface, leading to a partial compensation of substrate acceptors during N2O treatment and to an overcompensation during POCl3 annealing. Finally, cross-sectional SCM profiles performed on epitaxial n-doped 4H-SiC with 45 nm SiO2 (subjected to post deposition annealing in the two ambients) allowed to quantify the active donors concentrations associated to P or N incorporation under the gate oxide, showing almost a factor of ten higher doping (4.5×1018cm-3 vs 5×1017cm-3) in the case of P related donors.

The electrical compensation effect of the nitrogen incorporation at the SiO2/4H-SiC (p-type) interface after thermal treatments in ambient N2O is investigated employing both scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM). SSRM measurements on p-type 4H-SiC areas selectively exposed to N2O at 1150 °C showed an increased resistance compared to the unexposed ones; this indicates the incorporation of electrically active nitrogen-related donors, which compensate the p-type doping in the SiC surface region. Cross-sectional SCM measurements on SiO2/4H-SiC metal/oxide/semiconductor (MOS) devices highlighted different active carrier concentration profiles in the first 10 nm underneath the insulator–substrate interface depending on the SiO2/4H-SiC roughness.The electrically active incorporated nitrogen produces both a compensation of the acceptors in the substrate and a reduction of the interface state density (Dit). This result can be correlated with the 4H-SiC surface configuration. In particular, lower Dit values were obtained for a SiO2/SiC interface on faceted SiC than on planar SiC. These effects were explained in terms of the different surface configuration in faceted SiC that enables the simultaneous exposition at the interface of atomic planes with different orientations.

A study of the carbonization process and of a low temperature buffer layer on the Cubic Silicon Carbide (3C-SiC) epitaxial growth has been reported in this work. From this study it has been evidenced the importance of the C/H2 ratio and of the buffer layer process on the voids formation at the 3C-SiC/Si interface. From our study, the influence of the voids the wafer curvature is highlighted. It has been observed that decreasing the density of these voids, decreases the stress of the 3C-SiC film; consequently, the wafer curvature is reduced.

We report on the fabrication and performance of Si-based light sources. The devices consist of MOS structures with erbium (Er)-doped silicon rich oxide (SRO) film as gate dielectric. The devices exhibit electroluminescence (EL) at 1.54 μm at room temperature with a 0.2% external quantum efficiency. These devices show a high stability due to the silicon excess in the film. The Er-doped SRO films have been introduced in a Si/SiO 2 Fabry–Perot Microcavity in order to increase the spontaneous emission rate, the extraction efficiency and the spectral purity at the resonant wavelength. The active medium in the cavity has been electrically pumped and the conduction mechanisms have been analyzed. The EL spectra have also been acquired and compared with photoluminescence (PL) ones for the same resonant cavity light-emitting device (RCLED). The EL and PL peak intensities of the on-axis emission at the resonant wavelength are over 20 times above that of the similar Er-doped SRO film without a cavity. The Si-based RCLEDs exhibit different quality factors, ranging from 60 to 170. The spectra shape and intensity have been correlated with the quality factor. A high directionality of the emitted light, due to the presence of the resonant cavity, has also been observed: the overall luminescence is confined within 10° cone from the sample normal.

We report on the fabrication and performances of highly efficient Si-based light sources. The devices consist of MOS structures with erbium (Er) implanted in the thin gate oxide. They exhibit strong 1.54 μm electro-luminescence (EL) at 300 K with a 10% external quantum efficiency, comparable to that of standard light emitting diodes using III–V semiconductors. Emission at different wavelengths has been achieved incorporating different rare earths (terbium (Tb) and ytterbium (Yb)) in the gate dielectric. The external quantum efficiency depends on the rare-earth ions incorporated and ranges from 10% (for a Tb doped MOS) to 0.1% (for an Yb doped MOS). RE excitation is caused by hot electrons impact and oxide wearout limits the reliability of the devices. Much more stable light emitting MOS devices have been fabricated using Er-doped silicon rich oxide (SRO) films as gate dielectric. These devices show a high stability, with an external quantum efficiency reduced to 0.2%. In these devices, Er pumping occurs partially by hot electrons and partially by energy transfer from the Si nanostructures to the rare-earth ions, depending on Si excess in the film. Si/SiO 2 Fabry–Perot microcavities have been fabricated to enhance the external quantum emission along the cavity axis and the spectral purity of emission from the films that are used as active media to fabricate a Si-based resonant cavity light emitting diode (RCLED). These structures are fabricated by chemical vapour deposition on a silicon substrate. The microcavities are tuned at different wavelengths (nm): 540, 980 and 1540 (characteristic emission wavelengths, respectively, for Tb, Yb and Er). The reflectivity of the microcavities is about 97% and the quality factor ranges from 60 (for the cavity tuned at 980 nm) to 95 (for the cavities tuned at 540 and 1540 nm).

The structure and thermal stability in N-2 of hydrogen-terminated (100) silicon has been studied by X-ray photoemission spectroscopy, transmission electron microscopy, atomic force microscopy, thermal programmed desorption, and reflection high energy electron diffraction. Device-quality surfaces were prepared in an open-chamber reactor by exposing single crystalline, (100) oriented silicon to H-2 at high temperature (850 degreesC or 1100 degreesC) for durations on the order of 10(2) s. The observed stability with respect to N-2 at 850 degreesC is inconsistent with the reported desorption kinetics and may be accounted for in terms of either physico-chemical properties of the system (e.g., the presence of a buried layer of H-2 or of hydrogen-decorated vacancies whose out-diffusion restores the hydrogen terminations on the surface) or the reactor (persistence of hydrogen in the atmosphere even after switching it off). The nitridation by N-2 of hydrogen-terminated silicon is less efficient (per unit exposure) than that by N2O by 4 orders of magnitude.

The increasing interest for lightweight and portable electronic systems, cellphones and small digital devices is driving technological research towards integrated regenerating power sources with small dimensions and great autonomy. Conventional batteries are already unable to deliver power in ever smaller volumes while maintaining the requirements of long duration and light weight. A possible solution to overcome these limits is the use of miniaturized fuel cells. The fuel cell offers a greater gravimetric energy density compared to conventional batteries. The micromachining technology of silicon is an important tool to reduce the fuel cell structure to micron sizes. The use of silicon also gives the opportunity to integrate the power source and the electronic circuits controlling the fuel cell on the same structure. This article reports preliminary results concerning the micromachining process for fabricating a silicon-based electrocatalytic membrane for miniaturized Si-based proton-exchange membrane (PEM) fuel cells.

We report on the fabrication and characterization of Si/SiO 2 Fabry-Perot microcavities. These structure are used to enhance the external quantum emission along the cavity axis and the spectral purity of emission from Rare earth doped and undoped SiOx (x ≤ 2) films that are used as active media to fabricate a Si based RCLED (Resonant Cavity Light emitting Devices). These structures are fabricated by chemical vapour deposition on a silicon substrate. The microcavities are tuned at different wavelengths: 540 nm, 980 nm, 1540 nm, 780 nm and 850 nm (characteristic emission wavelength respectively for Tb, Yb and Er and Silicon Rich Oxide (SRO)). The reflectivity of the microcavities is of 97% and the quality factor ranges from 50 (for the cavity tuned at 540nm) to 95 (for the cavities tuned at 980 nm and 1540 nm) and 150 (for the cavity tuned at 780 nm and 850 nm). These cavities have been characterized by TEM analysis to evaluate film uniformity, thickness and densification after annealing process for temperature ranging from 800° to 1100°C. The reflectivity and photoluminescence spectra show resonant wavelengths in agreement with the calculated values. A new structure to electrically pump the active media has been designed. The electrical properties of the active media have been analysed. An enhancement of the photoluminescence signal of twenty times have been achieved for the selected emission wavelength.

The increasing interest for light and movable electronic systems, cell phones and small digital devices, drives the technological research toward integrated regenerating power sources with small dimensions and great autonomy. Conventional batteries are already unable to deliver power in more and more shrunk volumes maintaining the requirements of long duration and lightweight. A possible solution to overcome these limits is the use of miniaturized fuel cell. The fuel cell offers a greater gravimetric energy density compared to conventional batteries. The micromachining technology of silicon is an important tool to reduce the fuel cell structure to micrometer sizes. The use of silicon also gives the opportunity to integrate the power source and the electronic circuits controlling the fuel cell on the same structure. This paper reports preliminary results concerning the micromachining procedure to fabricate an arrays of microchannels for a Si-based electrocatalytic membrane for miniaturized Si-based proton exchange membrane fuel cells. Several techniques are routinely used to fabricate arrays of microchannels embedded in crystalline silicon. In this paper we present an innovative microchannel formation process, entirely based on surface silicon micromachining, which allows us to produce rhomboidal microchannels embedded on (100) silicon wafers. Compared to the traditional techniques, the proposed process is extremely compatible with the standard microelectronics silicon technology. The kinetics of rhomboidal microchannel formation is monitored by cyclic voltammetry measurements and the results are compared with a detailed structural characterisation performed by scanning electron microscopy. The effectiveness of this process is discussed in view of the possible applications in the fuel cell application.

Several techniques are routinely used to fabricate arrays of microchannels embedded in crystalline silicon. They are commonly based on plasma or anisotropic etch of silicon and on subsequent wafer bonding to close the cavities on top. These techniques are quite complex and usually work on (110) oriented silicon wafers. In this paper we present an innovative microchannel formation process, entirely based on front side wafer silicon bulk micromachining, which allows us to produce rhomboidal microchannels embedded on (100) silicon wafers. Compared to the traditional techniques, the proposed process is very compatible with the standard microelectronics silicon technology. The kinetics of rhomboidal microchannel formation are monitored by cyclic voltammetry measurements and the results are compared with a detailed structural characterization performed by scanning electron microscopy. The effectiveness of this process is discussed in view of the possible applications in the microfluidic field.

We report on the fabrication and performances of the most efficient Si-based light sources. The devices consist of MOS structures with erbium (Er) implanted in the thin gate oxide. The devices exhibit strong 1.54 μm electroluminescence at 300K with a 10% external quantum efficiency, comparable to that of standard light emitting diodes using III-V semiconductors. Emission at different wavelenghts has been achieved incorporating different rare earths (Ce, Tb, Yb, Pr) in the gate dielectric. The external quantum efficiency depends on the rare earth ions incorporated and ranges from 10% (for an Tb doped MOS) to 0.1% (for an Yb doped MOS). RE excitation is caused by hot electrons impact and oxide wearout limits the reliability of the devices. Much more stable light emitting MOS devices have been fabricated using Er-doped SRO (Silicon Rich Oxide) films as gate dielectric. These devices show a high stability, with an external quantum efficiency reduced to 0.2%. In these devices Er pumping occurs part by hot electrons and part by energy transfer from the Si nanostructures to the rare earth ions, depending by Si excess in the film. Si/SiO2 Fabry-Perot microcavities have been fabricated to enhance the external quantum emission along the cavity axis and the spectral purity of emission from the films that are used as active media to realize a Si based RCLED (resonant cavity light emitting diode). These structures are realized by chemical vapour deposition on a silicon substrate. The microcavities are tuned at different wavelengths: 540nm, 980nm and 1540nm (characteristic emission wavelengths respectively for Tb, Yb and Er). The reflectivity of the microcavities is of 97% and the quality factor ranges from 60 (for the cavity tuned at 980nm) to 95 (for the cavities tuned at 540nm and 1540nm).

The increasing interest for light and movable electronic systems, cell phones and small digital devices, drives the technological research toward integrated regenerating power sources with small dimensions and great autonomy. Conventional batteries are already unable to deliver power in more and more shrunk volumes maintaining the requirements of long duration and light weight. A possible solution to overcome these limits is the use of miniaturised fuel cell. The fuel cell offers a greater gravimetric energy density compared to conventional batteries. The micromachining technology of silicon is an important tool to reduce the fuel cell structure to micrometer sizes. The use of silicon also gives the opportunity to integrate the power source and the electronic circuits controlling the fuel cell on the same structure. This paper reports preliminary results concerning the micromachining procedure for fabricating a Si-based electrocatalytic membrane for miniaturised Si-based proton exchange membrane fuel cells (PEMFC).

Nitridation of hydrogen-terminated silicon in a diluted N2 : N2O atmosphere was studied by X-ray photoemission spectroscopy and high-resolution electron microscopy. Our analysis showed that the broad N(1s) peak of width 1.5 eV at 398-399 eV, usually reported in the literature, is preceded by the formation of a narrow peak of width around 1.0 eV at 397.5 eV, attributed to the moiety Si3N in which silicon is only marginally oxidized, and two other peaks at 400.0 eV and 401.5 eV, attributed to the moieties Si2NOSi and SiNO, respectively.

The early oxidation stages of hydrogen-terminated single-crystalline (100) silicon exposed to a diluted N2 : N2O atmosphere at 850°C for different durations have been studied by x-ray photoemission spectroscopy, following the evolution of the Si 2p signal. Evidence is given that the usual analysis, in terms of five pairs of peaks attributed to silicon in the oxidation states from 0 to +4, does not account for the observed Si 2p signal. An explanation for silicon in unusual oxidation states is proposed.

Nitridation of hydrogen-terminated silicon with N2:N2O has been studied by x-ray photoemission spectroscopy. Our analysis has given evidence that the broad N(1s) peak at 398–399 eV, usually reported in the literature, is preceded by the formation of a narrow peak at 397.5 eV, attributed to the moiety Si3N in which silicon is only marginally oxidized, and two other peaks at 400.0 eV and 401.5 eV, attributed to the moieties Si2NOSi and SiNO, respectively.

Oxynitridation of hydrogen-terminated silicon with N2O has been studied by x-ray photoemission spectroscopy. Our analysis has given evidence that the broad N(1s) peak at 398.3 eV usually reported in the literature is preceded by the formation of a very narrow peak at 397.3 eV, attributed to the moiety Si3N in which nitrogen is only marginally oxidized, and two other peaks (previously never reported) at 400.0 eV and 401.5 eV, attributed to the moieties Si2NOSi and SiNO, respectively.

not Available.

This paper reports on the physical and temperature-dependent electrical characterizations of the oxide/semiconductor interface in MOS capacitors with a SiO2 layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The capacitors, subjected to a standard post deposition annealing process in N2O, exhibited an interface state density Dit ≈ 9.0 × 1011 cm−2 eV−1 below the conduction band edge. At room temperature, a barrier height (conduction band offset) of 2.8 eV was observed, along with the presence of negative charges in the insulator. The SiO2 insulating properties were evaluated by studying the experimental temperature-dependence of the gate current. In particular, the temperature-dependent electrical measurements showed a negative temperature coefficient of the Fowler-Nordheim electron barrier height (dΦB/dT = − 0.98 meV/°C), which was very close to the expected value for an ideal SiO2/4H-SiC system and much lower compared to the values reported for thermally grown SiO2. This smaller dependence of ΦB on the temperature and the increase of the current level with temperature in the transcharacteristics measured in the relative fabricated MOSFETs represents a clear advantage of our deposited SiO2 for the operation of MOSFET devices at high temperatures.