185 results on '"Siriburanon, Teerachot"'
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2. Frequency Synthesis Technique for 60 GHz Multi-Gbps Wireless
3. A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness
4. A Gm -Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing
5. Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures
6. Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial
7. A Digital-to-Time Converter Based on Crystal Oscillator Waveform Achieving 86-fs Jitter in 22-nm FD-SOI CMOS
8. Flicker Phase-Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators
9. A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range
10. A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking
11. A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications
12. Cryogenic Controller for Electrostatically Controlled Quantum Dots in 22-nm Quantum SoC
13. An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS
14. A 50.1Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay with Calibration of LO Feed-Through and I/Q Imbalance
15. A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL
16. A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS
17. A 24–31 GHz Reference Oversampling ADPLL Achieving FoMjitter−N of -269.3 dB
18. Cryogenic Low-Drop-Out Regulators Fully Integrated with Quantum Dot Array in 22-nm FD-SOI CMOS
19. A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS
20. A Low Profile Highly Isolated Phased Array MIMO Antenna System for 5G Applications at 28 GHz
21. An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS
22. A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications
23. A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing
24. A Type-II Phase-Tracking Receiver
25. Oscillator Flicker Phase Noise: A Tutorial
26. A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N
27. Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS
28. Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K
29. Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process
30. RF Clock Distribution System for a Scalable Quantum Processor in 22-nm FDSOI Operating at 3.8 K Cryogenic Temperature
31. Time-Domain Multiply-Accumulator using Digital-to-Time Multiplier for CNN Processors in 28-nm CMOS
32. Design of a Non-Linear Sized I/Q Digital PA for 5G mm-Wave Communications in 28 nm CMOS
33. Charge Analysis in SAR ADC with Discrete-Time Reference Driver
34. A 265-µW Fractional-N Digital PLL with Switching Subsampling/Sampling Feedback
35. A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS
36. A Compact 0.2–0.3-V Inverse-Class-F 23 Oscillator for Low 1/ f 3 Noise Over Wide Tuning Range.
37. A Low-Power Low-Noise mm-Wave Sub-Sampling PLL using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad
38. 17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM
39. A Single-Electron Injection Device for CMOS Charge Qubits Implemented in 22-nm FD-SOI
40. A Tiny Complementary Oscillator With 1/f 3 Noise Reduction Using a Triple-8-Shaped Transformer
41. A 2.02–2.87-GHz −249-dB FoM 1.1-mW Digital PLL Exploiting Reference-Sampling Phase Detector
42. A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS
43. Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators
44. DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization
45. A 31-$\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS
46. A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip
47. 28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications
48. A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS
49. A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit
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