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This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 10-nm FinFET technology, the TX incorporates a four-way interleaved quarter-rate architecture with a three-tap feed-forward equalizer (FFE). Key features of the TX include a 1-UI pulse-generator-based 4:1 serializer combined with a current-mode logic (CML) driver, low-power data-serializing paths, an output pad-network using a multi-segment $\pi $ -coil for bandwidth co-optimization together with ESD diodes, sub-80-fs resolution duty-cycle detector/corrector (DCD/DCC) and quadrature-error detector/corrector (QED/QEC) circuits, and a hybrid LC -phase-locked loop (PLL) with quadrature clock distribution circuits. The TX operating at 112 Gb/s in PAM-4 modulation consumes 232 mW from 1- and 1.5-V supplies, achieving an 2.07 pJ/b energy efficiency. The TX front end occupies an area of 0.0302 mm2.

The rapidly growing demand for high-bandwidth data communication infrastructure has fueled the industry to develop ultra-high-speed/density wireline links compliant with electrical interface standards such as CEI-56G and 802.3bs–400GbE. Recent publications have demonstrated CMOS transmitters (TX) operating from 50–64Gb/s [1-4], and early planning for the next generation of 100Gb/s+ wireline standards is underway. Long-reach wireline standards at 56Gb/s have largely adopted a PAM-4 modulation scheme that maintains the same symbol rate as the previous generation of 28Gb/s NRZ transceivers. For 112Gb/s transceivers, however, higher order modulation (e.g., PAM-8/16) is unlikely to be adopted due to the tradeoff in SNR and backward compatibility. Therefore, the symbol rate for 112Gb/s PAM-4 must be doubled relative to the previous generation, which requires circuit bandwidth and jitter performance to improve by roughly a factor of two. In addition, the energy efficiency of the link must be maximized to keep local power delivery and system power consumption within practical limits. This paper presents a reconfigurable 56GS/s 3-tap FFE TX that operates up to 112Gb/s with PAM-4 or at 56Gb/s with NRZ modulation. The TX employs a quarter-rate architecture, a 1-UI pulse-generator-based 4:1 serializer combined with a CML driver, a multi-segment π-coil for pad bandwidth extension, and per-lane duty-cycle detection/correction (DCD/DCC) and quadrature-error detection/correction (QED/QEC) circuits. The TX is implemented in a 10nm FinFET CMOS technology and benefits from improvements to transistor drive strength, interconnect electro-migration/resistance, and overall area scaling [5].

It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90 nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the peicewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9 dB (without calibration) is achieved at 210 MSPS from the Verilog synthesized design.

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5 dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.

A low-power synthesizable analog-to-digital converter (ADC) is presented. By cascading many digital-like domino-logic cells whose propagation delay is influenced by an analog input voltage, a digital value is obtained at the end of the allowed ripple period by determining the number of cells that the ripple passed through. The sample-and-hold is simply a bootstrapped switch into a small sampling capacitor. As each domino-logic cell passes the ripple, charge is kicked back onto the input capacitor, which creates a significant second harmonic. Distortion caused by even harmonics is canceled by implementing a pseudodifferential structure. A test chip is fabricated in 0.18-μm CMOS. The test chip achieves over 5.4-bit effective number of bits up to 50 MS/s with a 1.3-V supply. With a sampling frequency of 50 MS/s and a 24-MHz input, a 34.2-dB signal-to-noise-plus distortion ratio is achieved while consuming 433 μW and occupying only 0.094 mm2.

A stochastic flash analog-to-digital converter (ADC) is presented. A standard flash uses a resistor string to set individual comparator trip points. A stochastic flash ADC uses random comparator offset to set the trip points. Since the comparators are no longer sized for small offset, they can be shrunk down into digital cells. Using comparators that are implemented as digital cells produces a large variation of comparator offset. Typically, this is considered a disadvantage, but in our case, this large standard deviation of offset is used to set the input signal range. By designing an ADC that is made up entirely of digital cells, it is a natural candidate for a synthesizable ADC. Comparator trip points follow the nonlinear transfer function described by a Gaussian cumulative distribution function, and a technique is presented that reduces this nonlinearity by changing the overall transfer function of the stochastic flash ADC. A test chip is fabricated in 0.18- CMOS to demonstrate the concept.

High-speed serial links integrated in advanced CMOS are ubiquitous in modern microprocessor systems. These commodity links have fixed performance specs and therefore realize the benefit of technology scaling in area and power reduction at high data rates. To realize significant scaling benefits, these designs must overcome the challenges associated with implementing analog functions in scaled logic-optimized processes while maintaining link robustness over a wide range of channel characteristics and third party components.

A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18µm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.

The relation between opamp noise and the size of the level shifting capacitor in correlated level-shifting (CLS) architectures is explored. Analysis is performed for a Split-CLS switched capacitor amplification circuit, and many of the conclusions in this paper are applicable to more general CLS architectures as well. A theoretical model for noise is developed and shown to be in good agreement with simulation. It is found that for practical design values, the size of the level-shifting capacitor only weakly influences noise performance.

A new correlated level shifting method with two level shifting operations is presented. It is shown to enable processing, with 9.1 ENOB accuracy, a signal 320mV greater than the 1.2V supply in a pipelined ADC when sampling at 21MHz and using only 2.8mW of power.

An optimized memory structure, Binary Access Memory (BAM), is presented for successive approximation applications that employ an error correction lookup table. Unlike true random-access memory, the probability of different codes occurring in a binary successive approximation access pattern is not uniformly distributed. BAM exploits this fact in several ways to reduce the number of sub-block switches, the average and worst-case access latency, and power consumption compared to a conventional SRAM lookup table. A simple technique for using BAM in an asynchronous successive approximation design is also presented.

The equation for calculating ENOB from SNDR of a sine-wave test is only accurate when noise is uncorrelated to the input. In this paper, the equation for calculating ENOB from SNDR is derived for an ideal and a uniform stochastic ADC. The result of these derivations shows that calculating ENOB from SNDR using the conventional equation causes a better-than-actual result in the case a uniform stochastic ADC.

A circuit is presented that halves the number of comparators required for a two-group stochastic flash ADC. In a two-group stochastic flash ADC, two Gaussian PDFs are shifted left and right by applying a global offset reference to the two groups of comparators. This creates a virtual uniform distribution of comparator offset between the two global offsets. Over half of the comparators fall outside of the virtual uniform distribution and are not used. The proposed circuit inverts the polarity of each comparator offset until it is within the useful range, creating a virtual uniform distribution of comparator offsets with few comparators wasted.

A new single-loop delta-sigma modulator with extended dynamic range is proposed. It employs an auxiliary multi-bit quantizer which processes the quantization error of the main quantizer. This addition guarantees improved stability over a wider input signal range. The cancelation of the quantization noise of the main quantizer is done via in-loop digital summation and is immune to opamp DC gain. As a proof of concept, a 3rd order modulator is designed in a 0.18µm CMOS process. This implementation incorporates a 3-level main quantizer, a 9-level auxiliary quantizer and 30dB open-loop opamp gain. Measurement results show that at 1.2V power supply and reference, the input signal can go over +5dBFS without any stability issues, achieving 75dB SNDR and 77.2dB dynamic range at OSR of 16. The clock frequency is 40MHz and the power dissipation is 4.9mW.

A ones adder is an important circuit block that is required in many varying applications. This work proposes a design that largely relies on passive transmission-gate multiplexers. Many variations are suggested that can inherently generate a thermometer coded output or one-hot encoded output. The proposed structure has area and power that increases with order n 2 for a n number of inputs. A folding technique is then suggested that reduces the area/power to order n log(n). The folded passive linear counter also has a cell-based structure that aids in layout and makes it possible to be added to a digital standard cell library.

A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.

Using knowledge of the random nature of device mismatch it is possible to employ stochastic techniques in an ADC. This would allow the use of many smaller and less accurate components, and may make it possible to save power and area while maintaining accuracy. Additional benefits include high scalability and high yield with process variation. Various design considerations are suggested that must be addressed to design a successful stochastic ADC and an example calibration and decoding scheme is described.