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Band-to-band tunneling was studied in ion-implanted P/N junction diodes with profiles representative of present and future silicon complementary metal-oxide-silicon (CMOS) field effect transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of capacitance versus voltage characteristics, and compared to secondary-ion mass spectroscopy analysis. When the tunneling current was plotted against the effective tunneling distance (tunneling distance corrected for band curvature) a quasi-universal exponential reduction of tunneling current versus, tunneling distance was found with an attenuation length of 0.38 nm, corresponding to a tunneling effective mass of 0.29 times the free electron mass (m 0), and an extrapolated tunneling current at zero tunnel distance of 5.3× 10 7 A/cm² at 300 K. These results are directly applicable for predicting drain to substrate currents in CMOS transistors on bulk silicon, and body currents in CMOS transistors in silicon-on-insulator. [ABSTRACT FROM AUTHOR]

• Analog techniques can accelerate machine learning by orders of magnitude. • Multiple strategies, by analog designers, bypass limitations of analog devices. • Examples are based on current work at IBM. Digital logic technology has been extraordinarily successful and has been fueled by incredible gains in integration density and performance achieved over the years following Moore's law. This has led to societal changes where more and more everyday functions are aided by smart devices following the path to artificial intelligence. However, in the field of deep machine learning, even this technology falls short, partly because device scaling gains are no longer easy to come by, but also due to intractable energy costs of computation. Deep learning, using labeled data, can be mapped onto artificial neural networks, arrays where the inputs and outputs are connected by programmable weights, and which can perform pattern recognition functions. The learning process consists of finding the optimum weights however this learning process is very slow for large problems. Exploiting the fact that weights do not need to be determined with high precision, as long as they can be updated precisely, the device community has recognized that analog computation approaches, using physical arrays of memristor (programmable resistor) type devices could offer significant speedup and power advantages compared to pure digital, or pure software approaches. On the other hand, the history of analog computation is not reassuring since the rule has been that more capable digital devices invariably supplant analog function. In this paper I will discuss the opportunities and limitations of using analog techniques to accelerate the learning process in resistive neural networks. [ABSTRACT FROM AUTHOR]

It has recently been suggested that ferroelectric (FE) negative capacitance effects can be used to achieve steep subthreshold slope field-effect transistors, which are greatly desired for reducing energy consumption in modern digital electronics. Here, we propose that this concept can be improved by the introduction of a very thin metal or metal-like layer (a quantum metal) between the FE and the semiconductor channel. We show how to design this layer so that it attenuates the polarization charge of the FE, applying an appropriate charge to the semiconductor, while at the same time presenting a relatively constant capacitance to the FE layer, as is needed to stabilize the negative capacitance regime. For homogeneous polarization, we estimate that this device (a QMFeFET) can have extremely steep subthreshold characteristics (2 mV/decade over 11 decades) and that its energy and delay performance are advantageous. [ABSTRACT FROM AUTHOR]

Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse—probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ∼50 mK, a time resolution of 5 ns, and a temperature sensitivity of ∼0.6 μA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental—simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. [ABSTRACT FROM AUTHOR]

Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate con- trol than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum con- finement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a (001)-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. [ABSTRACT FROM AUTHOR]

In the article the authors reflect on increasing the speed of computers by improving field-effect transistors. They assert that electronic companies are shrinking the transistor and increasing the number of parallel processors which results in power dissipation and heat generation. They opine that improving the operation of transistors means altering the switching behavior so less gate voltage is needed to turn the device on and off.

Many in the microelectronics field view tunneling field-effect transistors (TFETs) as society's best hope for achieving a >10× power reduction for electronic devices; however, despite a decade of considerable worldwide research, experimental TFET results have significantly underperformed simulations and conventional MOSFETs. To explain the discrepancy between TFET experiments and simulations, we investigate the parasitic leakage current due to Auger generation, an intrinsic mechanism that cannot be mitigated with improved material quality or better device processing. We expose the intrinsic link between the Auger and band-to-band tunneling rates, highlighting the difficulty of increasing one without the other. From this link, we show that Auger generation imposes a fundamental limit on ultimate TFET performance. [ABSTRACT FROM AUTHOR]

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored. [ABSTRACT FROM AUTHOR]

The article reports that the excellent electrical properties of single-walled carbon nanotubes (SWCNT) make them the most promising candidate for creating transistors on a scale smaller than can be achieved with silicon. A field-effect transistor (FET), which is the basic component of present computer circuitry, has been demonstrated based on individual SWCNTs. This achievement would demonstrate that SWCNTs can be used as a basis for electronics, similar to the way silicon wafers are currently used. A ring oscillator is the ultimate test for new materials in high-frequency ac applications and for evaluating their compatibility with conventional circuit architectures. In a CMOS inverter, both an n-type FET and a p-type FET are needed to realize a basic logic function. An extra inverter stage, which eliminates interference between the measurement setup and the oscillator operation, follows the ring oscillator portion to allow for the signal to be read by a spectrum analyzer.