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9 results on '"Son, Yunik"'

1. Improved Technique for Extraction of Effective Mobility by Considering Gate Bias-Dependent Inversion Charges in a Floating-Body Si/SiGe pMOSFET

Author

Bae, Hagyoul, primary, Bang, Tewook, additional, Kim, Choong-Ki, additional, Hur, Jae, additional, Kim, Seyeob, additional, Jeon, Chang-Hoon, additional, Park, Jun-Young, additional, Ahn, Dae-Chul, additional, Kim, Gun-Hee, additional, Son, Yunik, additional, Lee, Jae-Hoon, additional, Kim, Yong-Taik, additional, Ryu, Seong-Wan, additional, and Choi, Yang-Kyu, additional

Published
2017
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2. Diffusion and Gate Replacement: A New Gate-First High- $k$ /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry

Author

Ritzenthaler, Romain, primary, Schram, Tom, additional, Spessot, Alessio, additional, Caillat, Christian, additional, Cho, Moonju, additional, Simoen, Eddy, additional, Aoulaiche, Marc, additional, Albert, Johan, additional, Chew, Soon-Aik, additional, Noh, Kyoung Bong, additional, Son, Yunik, additional, Mitard, Jerome, additional, Mocuta, Anda, additional, Horiguchi, Naoto, additional, Fazan, Pierre, additional, and Thean, Aaron Voon-Yew, additional

Published
2016
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9. A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond.

Author

Ritzenthaler, Romain, Schram, Tom, Spessot, Alessio, Caillat, Christian, Aoulaiche, Marc, Cho, Moon Ju, Noh, Kyoung Bong, Son, Yunik, Na, Hoon Joo, Kauerauf, Thomas, Douhard, Bastien, Nazir, Aftab, Chew, Soon Aik, Milenin, Alexey P., Altamirano-Sanchez, Efrain, Schoofs, Geert, Albert, Johan, Sebai, Farid, Vecchio, Emma, and Paraschiv, Vasile

Subjects
COMPLEMENTARY metal oxide semiconductors, DYNAMIC random access memory, STRAY currents, LOGIC circuits, METAL oxide semiconductor field-effect transistors, THERMAL stability
Abstract

In this paper, a low-cost and low-leakage gate-first high- \(k\) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 \(\mu \) A/ \(\mu \) m can be obtained for an OFF-state current of \(10^{-10}\) A/ \(\mu \) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability. [ABSTRACT FROM AUTHOR]

Published
2014
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