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Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique.

Advanced interconnects development requires introduction of porous ultra low k (ULK) dielectrics enhancing product performance through parasitic capacitance reduction. ULK layers are characterized by higher carbon content and lower mechanical properties due to porosity increase. Consequently, ULK dielectrics are more prone to be damaged during plasma treatment in interconnects build [1]. Pre-clean processes prior to barrier/seed deposition are a potential area of concern for ULK integrity. Reactive pre-clean processes based on He/H"2 plasma are investigated in this paper through two types of hardware. The new pre-clean chamber is an upgrade of conventional pre-clean hardware and combines optimized H"2 plasma and active wafer temperature control to ensure efficient copper oxide reduction [3] and via cleaning. The aim of the paper is to evaluate performance of the new generation of reactive pre-clean compared to conventional hardware. To overcome ULK dielectric integration challenge, pre-clean processes need to ensure efficient copper oxide reduction and via bottom cleaning with minimum impact on ULK material properties. The ''new reactive pre-clean'' addresses these requirements for k=2.5 ULK materials. The new reactive pre-clean demonstrates a robust process window over a wide range of temperature and pressure settings for all characterized aspects. The ''new reactive pre-clean'' technology is seen to be a promising pre-clean candidate for next generation of porous ULK dielectric material ([email protected]?2.5) integration for 28nm node and beyond.

Two seed deposition hardware are compared in this paper: a standard Self Ionized Plasma (SIP) standard chamber and a new generation chamber allowing Cu deposition and re-sputtering simultaneously. TEM characterizations exhibits better features coverage for new seed generation thank to process fine tuning. It induces defectivity improvement and void density is reduced with new hardware. Furthermore, reliability performances are improved without degrading parametrical results.

A 32nm node BEOL integration scheme is presented with 100nm metal pitch at local and intermediate levels and 50nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32nm RC performance specifications, extreme low-k (ELK) porous SiOCH k=2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k=2.3 is investigated using a multi-level metallization test vehicle in a 45nm mature generation.

A 32 nm node BEOL demonstrator using Trench First Hard Mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK k=2.3 & k=2.2 are studied in a TFHM architecture in order to prove its extendibility to ELK dielectric materials.

The paper deals with the introduction of an innovative self-aligned capping layer leading to the formation of a Cu/Si/N mixed interface. The process was first developed targeting the aggressive 65 nm technology node and below. After optimisation, the process was successfully introduced in a well known Cu/FSG integration scheme prior to SiN etch stop layer deposition; process interest and maturity was demonstrated on 300 mm wafers in a 110 nm technology node by showing both its full compatibility with industrial requirements for stabilized technology and clear performance improvements in terms of electrical performance, defectivity and resistance to electromigration. These results open large perspectives for the integration of a Si-based self-aligned barrier on Cu lines, the process capability covering several technology nodes used either in addition to thin dielectric barriers or as a single capping of the copper lines.

Due to the continuous shrink of technology dimensions, parasitic propagation delay time and crosstalk at interconnect levels increasingly affect overall circuit performances. New materials, processes and architectures are now required to improve BEOL performances. A rigorous high-frequency electromagnetic approach including the scattering effects on Cu line resistance was developed for coupled narrow interconnects to analyze the actual benefits of these innovations for different signal types covering application range from logic to I/O. Effects of advanced metallization (ALD thin barriers), low-k insulators (porous ULKs, low-k barriers), and innovative architectures (hybrid stacks, air gaps, self-aligned barriers) on signal propagation performance were quantified, resulting in an effective process selection for the 45 nm technological node and below.

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