Search

This work studies the single-event leakage current (SELC) degradation and the damage mechanism of the 4H-silicon carbide (SiC) p-i-n (PiN) diodes through experiments and simulations. Experimental results show that material damage near the p+/n− junction and metal damage at the p+/metal interface are observed in the near-surface region of the PiN diode after single-event radiation. The simulation results suggest that the transient strong electric field and high temperature near the p+/n− junction may cause these damages and eventually lead to SELC degradation. Based on the mechanism analyses, the new PiN diodes with multitype buffer layers (MBLs-PiN) are proposed. The results show that the simulated SELC threshold of MBLs-PiN is improved by a factor of about 2 compared with that of conventional PiN diodes (C-PiN).

Gallium oxide (Ga2O3) p–n heterojunctions play an important role in addressing the difficulties in Ga2O3p-type doping. Therefore, an efficient and economical fabrication method needs to be established to create single-crystal Ga2O3heterojunctions for device applications. In this work, we successfully achieved epitaxial growth of single-crystal nickel oxide (NiO) and β-Ga2O3heterojunctions based on the low-cost and vacuum-free mist chemical-vapor deposition. The full width at half maximum of the X-ray diffraction rocking curves of NiO (111) and β-Ga2O3(−201) reached 0.077° and 0.807°, respectively. The energy band between NiO and β-Ga2O3has a Type II heterojunction. Finally, we prepared a quasi-vertical diode based on the NiO/β-Ga2O3heterojunction, which exhibits obvious rectification characteristics of the p–n junction and provides a reverse breakdown voltage of 117 V. This work proposes a low-cost fabrication method for β-Ga2O3p–n heterojunctions.

The design of device termination is crucial for power devices. In this letter, we present a novel approach for designing termination in Si-based power devices using deep neural networks (DNN), taking the narrowed field-limiting ring (NFLR) as an example. Our proposed method can not only achieve a prediction accuracy of over 97% for breakdown voltage (BV), but also provide the device optimization design scheme automatically and intelligently. We believe that the proposed machine learning technology can significantly reduce the cost and enhance the efficiency of power device design, establishing itself as a promising method for power device design.

In this paper, a novel modulation method is proposed for the torque ripple suppression of a brushless DC motor (BLDCM) during both the commutation period and the speed regulation period. The main sources of torque ripple are the imbalance current during commutation and the PWM during speed regulation. A single-inductor multiple-output (SIMO) Buck DC–DC converter is adopted to generate input voltage for the inverter driver of a BLDCM. During the commutation period, the input voltage of an inverter can be adjusted to four times the back electromotive force (EMF), which suppresses the torque ripple caused by imbalance commutation current. Meanwhile, by changing the output voltage of a SIMO DC–DC, the speed of a BLDCM can be regulated without PWM on the inverter switches, which also suppresses the torque ripple. A control algorithm is applied on a Field Programmable Gate Array (FPGA), and the proposed BLDCM drive prototype is fabricated and tested. Measurement results show that with the proposed speed regulation strategy, the torque ripple is suppressed from 33.3% to 20.1%, and that with the proposed suppression strategy in commutation, the torque ripple is suppressed further to 5.3%.

When silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) operate in the third quadrant, the surge current under extreme operating conditions hinders the body diode from replacing the external SiC Schottky barrier diode (SBD) as the freewheeling diode. Primarily, the channel activation of SiC MOSFET at ${V}_{\text {GS}}$ = 0 V is attributed to the body effect and the current conduction pathway within the p-well. Following this, an in-depth surge reliability analysis is conducted, contingent upon the varying structures of SiC MOSFET. The experimental result indicates that the surge capability of double-trench SiC MOSFET is inferior compared with planar SiC MOSFET and asymmetric SiC MOSFET. The impurity defects by the deep groove process and the design of the terminal layout are the critical constraints to the reliability of D-MOSFET under surge current stress. The interplay of static parameter degradation and scanning electron microscopy (SEM) investigations pinpoints two primary factors accountable for device failure. On the one hand, the gate and source terminals are short circuited due to the melting of metal electrodes caused by substantial surge currents. On the other hand, severe thermomechanical strains, incited by elevated thermal stresses attributable to surge currents, provoke substrate fissuring, and culminating in comprehensive short circuits bridging the gate, source, and drain terminals.

In this letter, high-performance 4H-SiC junction barrier Schottky diodes with state-of-art single-pulse avalanche energy density by adopting recessed anode and termination regions structures have been demonstrated. With effective alleviation of avalanche current crowding effect at the boundary, near uniform distribution of avalanche breakdown was achieved. During the avalanche reliability evaluation in the inductive load circuits, crucial avalanche capability with EAS is up to 10.7 J/cm2. There are no parametric drift and device degradation after enduring more than 1 000, 000 repetitive clamping pulses were performed at EAS = 6.0 J/cm2, showing great potential for high-power and high-reliable power conversion.