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The High Luminosity upgrade for the Large Hadron Collider LHC (HL-LHC) requires new Nb3Sn superconducting magnets and it triggers a development of novel hardware for the quench detection system (QDS) based on a field programmable gate array (FPGA) digital platform and a number of individually isolated analogue front-ends. Galvanic insulation has been implemented downstream the analogue to digital convertors to eliminate a usage of analogue isolation amplifiers. This concept was already successfully implemented in the current LHC QDS system, however the mitigation of new phenomena inside Nb3Sn materials required development of a new generation of QDS. The newly developed universal QDS offers flexibility of firmware defined architecture. Adopted prototype driven strategy includes thorough characterization of the analogue front-ends in the laboratory and prototype unit measurements performed on HL-LHC magnet prototypes at CERN's superconducting magnet test facility SM18. The tests also reveal the characteristics of the magnets as well as the measurement electronics at an early stage. The test results are used to optimize the analogue input stages as well as the digital signal processing within the FPGA. The preliminary test results are presented and focus is given to the measurement and studies of the so-called “flux jumps” to mitigate the effects of these voltage perturbations in the QDS.

High Level Synthesis takes an abstract behavioural or algorithmic description of a digital system and creates a register transfer level structure that realises the described behaviour. Various methodologies have been developed to perform such synthesis tasks. This paper presents the different HLS concepts used in the current leading tools. It makes a comparison between the different approaches and highlights their advantages and limitations. We also present a high level synthesis example.