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Typically, research and development (R&D) results of epitaxial layer growth show superior properties of the grown layers compared to high volume results. Layer uniformities are excellent and achieved defect densities are low compared to typical results. In particular, the conversion of basal plane dislocations (BPD) from the silicon carbide (SiC) substrate is in focus to reduce bipolar degradation of p-n-junctions. It is a great challenge to maintain those excellent results in high-volume manufacturing considering all the factors that impact the properties of the epilayer. Thus, quality of the layers, high throughput and low cost have to be assessed to find a compromise between these key factors. In this paper we present results on the growth of epitaxial layers on 150 mm and 200 mm 4° off-oriented 4H-SiC substrates using warm-wall multi-wafer chemical vapor deposition (CVD) systems. Single wafer data of the key epitaxial layer parameters, thickness, doping and defect densities, are compared to batch and lot results, as well as to statistical data of several hundreds of wafers produced. Improvements in wafer-to-wafer (w-t-w) doping uniformity could be achieved for instance by implementation of an on-wafer temperature measurement. Substrate impact on defect levels is shown comparing X-ray topography (XRT) results of bare substrate wafers and defect analysis of epilayers on sister wafers from the same crystal. Statistical defect data and resulting predicted yield loss also show a dependence on substrate suppliers. For the first time we show w-t-w and run-to-run (r-t-r) results of doping and thickness measurements on 200 mm substrates. Also, defect results of epilayers on 200 mm wafers are compared to results on 150 mm.

The quality of the silicon carbide (SiC) epitaxial layer, i.e., layer homogeneities and extended defect densities, is of highest importance for high power 4H-SiC trench metal-oxide-semiconductor field effect transistors (Trench-MOSFET) devices. Especially, yield for devices with a large chip area is severely impacted by extended defects. Previously, devices had to be fully manufactured to effectively gauge the impact of a reduction in extended defect densities in the epitaxial layers on device yield. The production of devices such as Trench-MOSFETs is an extensive procedure. Therefore, a correlation between extended defects in the epitaxial layer and electrical device failure would allow to reliably estimate the impact of process changes during epitaxial layer deposition on electrical device yield.For this reason, n-type epitaxial layers were grown on around 1,000 commercially available 150 mm 4H-SiC Si-face substrates, which received a chemical wet cleaning prior to the epitaxy deposition. Substrates with lowest micro-pipe density from two different suppliers were used. The wafers were characterized with the corresponding device layout for defects utilizing surface microscopy as well as ultraviolet photoluminescence techniques. Subsequently, these wafers were used to produce more than 500,000 Trench-MOSFET devices. All devices have been tested on wafer level for their initial electrical integrity.With these methods a precise correlation between extended defects in the epitaxial layer and electrical failures on wafer level could be found. The influence of different substrates on the defect-based yield prediction regarding the electrical yield on wafer level is discussed. Additionally, a calculated kill-ratio is presented and the severity of defect classes on initial device failure, e.g., stacking faults, and their key failures modes are discussed.