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Hot-carrier-induced degradation of short p-channel field-effect transistors in the presence of externally applied vertical mechanical force is investigated. The mechanical stress was induced in the devices by applying a normal load with a nanoindenter. Using finite element modeling, the induced stress to the channel was estimated to reach GPa range. It is shown that compressive mechanical stress considerably enhances the impact ionization rate and the generation of secondary electron-hole pairs. These can be trapped in the gate oxide and cause a hot-electron-induced punch-through effect and effective p-channel length reduction even after both mechanical and electrical stresses are removed. The presented findings indicate the importance of mechanical stress control and engineering for improving the device reliability.

We report measurements of multiple hot-carrier (HC) stress and high-temperature anneal cycles repeated on the same nFETs fabricated in a commercial 40-nm bulk CMOS technology. We model this cycled HC degradation anneal assuming Si–H bond breakage during stress and bond passivation during anneal, with the bond dissociation and passivation energies following a bivariate Gaussian distribution. Our model can describe multiple stress and anneal time scenarios well using a single parameter set and provides insights into the recovery behavior of HC-induced defects. We find no correlation between bond dissociation and passivation energies and observe that the repeated HC stress and anneal cycles suppress the low energies from the distribution of bond passivation energies, changing its shape from the Gaussian to a non-Gaussian form.

Using the deterministic version of our hot-carrier degradation (HCD) model, we perform a statistical analysis of the impact of random dopants (RDs) on the HCD in n-FinFETs. For this, we use an ensemble of 200 transistors with different configurations of RDs. Our analysis shows that changes in the linear drain currents have broad distributions, thereby resulting in broad distributions of device lifetimes. While lifetimes are nearly normally distributed at high stress biases, under voltages close to the operating regime, the distribution has a substantially different shape. This observation considerably complicates extrapolation from accelerated stress conditions, thereby suggesting that a comprehensive statistical treatment of the impact of RDs is required.

Silicon-hydrogen bonds play a crucial role in modern microelectronics, especially regarding reliability. At the semiconductor-oxide interface these bonds are broken via interaction with energetic charge carriers, which spoils a MOSFET's performance, for example. This study develops a consistent physical picture of that phenomenon through a bottom-up approach based on quantum mechanical formulations, and also unravels the disparity of that effect in $n\ensuremath{-}$ and $p\ensuremath{-}$MOSFETs. The model is free of empirical parameters and can easily be extended to emerging material combinations.

The continued challenge of front-end-of-line transistor reliability has long demanded physics-based SPICE compact models, not only for service lifetime estimation, but also for aging-aware device pathfinding with technology scaling and innovation. Here, we present a predictive hot-carrier-degradation (HCD) compact model built upon the industry-standard BSIM model, that conveniently embeds the essential HCD physics within common SPICE simulation flows. We leverage and augment the established, scalable electrostatics and transport in BSIM as the input to an analytical HCD interface states generation formalism, the result of which is in turn injected back into BSIM for a self-consistent estimation of the threshold voltage ( $V_{TH}$ ) shift and the mobility degradation. Our approach readily exhibits fundamental, non-empirical predictabilities of the stress time- and the sensing bias- dependency of transistor-level degradation, without having to resort to a priori assumptions. This will further accommodate the irregular, arbitrary voltage waveforms in transient circuit operations, thus enabling efficient evaluation of the power-performance degradation at circuit level. The model ultimately aims to lay the groundwork for a reliability-aware design-technology co-optimization in device pathfinding.

We report simulations of localized defect profiles (DPs), typical for hot-carrier degradation (HCD), with exponential- and step-like shapes. First, we analyze how these localized DPs affect the transistor I-V and model the complex relation between DP and FET degradation by considering the degraded FET as a series circuit of an undegraded transistor (the source side) and a degraded one (the drain side). We also compare how the same DP causes different degradation for changes in the device structure. Second, we use the DP simulations to qualitatively understand the DP dependence on stress voltages in measured FETs and assess how uniquely a DP can be extracted from degraded I-V metrics. The results are of interest for HCD modeling.

4H-SiC MOSFETs exhibit a hysteresis of the transfer characteristics due to electrically active traps near the $\mathrm{S}\mathrm{i}\mathrm{C}/\mathrm{S}\mathrm{i}\mathrm{O}_{2}$ interface. Our measurements, conducted within the temperature range of 150-260K revealed an interesting behavior, namely a notable decreasing hysteresis width towards higher T. During the up-sweep of gate voltage $V_{\mathrm{g}\mathrm{s}}$ curves are shifted towards higher gate voltages compared to the curves acquired at the down-sweep of $V_{\mathrm{g}\mathrm{s}}$. This implies that more traps are negatively charged at higher $V_{\mathrm{g}\mathrm{s}}$ conditions, and we attribute this behavior to acceptor-like border traps in oxide having its charge transition level 0/-1 near the SiC conduction band edge. To model electron capture and emission events of these oxide traps, we use the non-radiative multiphonon model. We calculate the capture and the emission times. The temperature dependence of the latter is the dominant feature which decreases the hysteresis width with increasing T. Our modeling approach is capable of reproducing the hysteresis width over the measured T range with good accuracy.

We develop and validate a physics-based modeling framework for coupled hot-carrier degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice temperature distribution throughout the device by solving the lattice heat flow equation coupled with the drift-diffusion approach. Then, the evaluated temperature spatial profile in the transistor is taken into account while solving the Boltzmann transport equation for carriers to obtain the carrier energy distribution functions, which are needed to compute the rates of the single-and multiple-carrier mechanisms of bond dissociation. The effect of SH on HCD is threefold: ( $i$ ) it results in a significant distortion of the carrier distribution function, (ii) device heating decreases vibrational lifetime of the Si-R bond, thereby suppressing the multiple-carrier mechanism, and (iii) the rate of thermal bond-breakage becomes higher due to SH. The model is capable of accurately reproducing relative changes in the saturation drain current with stress time measured in p-channel nanowire field-effect transistors subjected to HCD under different stress conditions. We show that neglecting SH leads to substantial underestimation of HCD.

We observe that non-zero gate bias applied during a high temperature anneal following hot-carrier degradation (HCD) impacts degradation recovery in nFETs. The devices are arranged into custom-built arrays and fabricated in a commercial 40 nm bulk CMOS technology and the FET anneal is induced by on-chip poly-Si heaters. The anneal is modeled using Stesmans' passivation model for Pb-defects in hydrogen gas (H2). Negative gate bias improves the anneal, in line with studies on biased passivation of process-induced Pb-defects.

We develop and validate a fully analytical model for hot-carrier degradation based on a thorough description of the physical picture behind this reliability phenomenon. This approach captures and links carrier transport, modeling of the Si-H bond-breakage mechanisms, and simulations of the degraded devices. All quantities evaluated within the model are described by analytical expressions and time consuming TCAD simulations are therefore avoided. We show that the model can capture measured dependencies of the normalized linear drain current change on stress time with good accuracy.

The effect of the geometric parameters of Fin field-effect transistors (FinFETs) on hot-carrier degradation (HCD) in these devices is theoretically studied. To this end, a model is used, in which three subproblems constituting the physical phenomenon of HCD are considered: carrier transport in semiconductor structures, description of microscopic defect formation mechanisms, and simulation of degraded device characteristics. An analysis is performed by varying the gate length, fin width and height. It is shown that HCD becomes stronger under fixed stress conditions in transistors with shorter channels or wider fins, while the channel height does not substantially affect HCD. This information can be important for optimizing the architecture of transistors with the fin-shaped channel to suppress degradation effects.

For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices.

A detailed simulation of degradation (caused by hot charge carriers) based on self-consistent consideration of the transport of charge carriers and the generation of defects at the SiO2/Si interface is carried out for the first time. The model is tested using degradation data obtained with decananometer n-type-channel field-effect transistors. It is shown that the mutual influence of the above aspects is significant and their independent simulation gives rise to considerable quantitative errors. In calculations of the energy distribution for charge carriers, the actual band structure of silicon and such mechanisms as impact ionization, scattering at an ionized impurity, and also electron–phonon and electron–electron interactions are taken into account. At the microscopic level, the generation of defects is considered as the superposition of single-particle and multiparticle mechanisms of breakage of the Si–H bond. A very important applied aspect of this study is the fact that our model makes it possible to reliably assess the operating lifetime of a transistor subjected to the effects of “hot” charge carriers.

We extend our previously suggested drift-diffusion (DD)-based hot-carrier degradation model to the case of decananometer transistors. Special attention is paid to the effect of electron-electron scattering, which populates the high energy tail of the carrier distribution function, by using a rate balance equation. We compare the results of the DD-based model with the results obtained from a spherical harmonics expansion of the Boltzmann transport equation as well as experimental data. We also study the accuracy and limits of the applicability of the DD-based model and conclude that this model is able to capture hot-carrier degradation in nMOSFETs over a range of gate lengths from 65 to 300 nm with excellent accuracy.

The IEEE International Integrated Reliability Workshop (IIRW) is a unique event that takes place every year at the beautiful Fallen Leaf Lake, in Tahoe, California. This workshop brings together reliability engineers and researchers from around the world, to exchange ideas over four days in a relaxed, friendly, and informal atmosphere. The workshop focuses on the recent advances in research concerning semiconductor device reliability and its different challenges. Topics include front-end-of-line reliability issues (bias temperature instability, hot-carrier degradation, time dependent dielectric breakdown), back-end-of-line/middle-of-line degradation effects (electromigration, stress migration, time dependent dielectric breakdown) as well as memory reliability, chip to package interaction, degradation effects in wide-bandgap-materials and high-voltage devices, and many others.

A unified compact modeling framework of device aging is proposed and verified on FinFET technology. For this purpose, the simplified EKV (sEKV) model is used for modeling the transfer characteristics and converting the stress current into carrier velocity-electric field profile. By combining this profile with TCAD simulations of the electric field along the channel, a simplified device representation consisting of a series of channel slices is constructed, which facilitates 2D degradation modeling performed in each slice by integrating oxide charge trapping, interface degradation due to Si-H bond breaking, and impact ionization. Our approach allows accurate reliability-enabled compact modeling across the entire bias space. Good agreement between experimental and simulated transfer characteristics is achieved. The calibrated model further reveals the complex interplays between different degradation mechanisms, consistent with previous reports.

Transistors fabricated on SiC substrates show superior properties for their application in high-power electronics. However, the performance of SiC MOSFETs in general can still not be completely exploited yet due to a higher defect density compared to Si/SiO 2 based devices. The defects give rise to a distinct hysteresis in the transfer characteristics and increased drifts of the threshold voltage over time, i.e. bias temperature instabilities, making accurate time-to-failure analysis more challenging. In our work we carefully analyze lateral channel SiC MOSFETs utilizing measure-stress-measure (MSM) schemes. To explain the experimental data we perform physics based device simulations considering the impact of a large set of single defects employing a two-state non-radiative multiphonon defect model. This approach allows us to extract defect bands for electron and hole trapping and to link them to possible defect structures proposed in the literature. Additionally, we compare simulation results employing our extracted trap bands with MSM data measured on vertical channel devices. Finally, an accurate lifetime prediction at operating conditions is presented.

We investigate correlation between linear drain currents (I d,lin ) in unstressed n-channel FinFETs and relative I d,lin changes (ΔI d,lin ) during hot-carrier degradation (HCD). For this analysis we simulate 200 different realizations of a FinFET where each of these devices has its own unique distribution of random dopants. Our study shows that devices with superior performance (with higher time-zero I d,lin values) degrade faster than initially “worse” transistors (with lower initial I d,lin currents) and, correspondingly, device lifetime also decreases with the time-zero I d,lin .