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Associative memory plays a crucial role in the cognitive capabilities of the human brain. The Bayesian Confidence Propagation Neural Network (BCPNN) is a cortex model capable of emulating brain-like cognitive capabilities, particularly associative memory. However, the existing GPU-based approach for BCPNN simulations faces challenges in terms of time overhead and power efficiency. In this paper, we propose a novel FPGA-based high performance computing (HPC) design for the BCPNN-based associative memory system. Our design endeavors to maximize the spatial and timing utilization of FPGA while adhering to the constraints of the available hardware resources. By incorporating optimization techniques including shared parallel computing units, hybrid-precision computing for a hybrid update mechanism, and the globally asynchronous and locally synchronous (GALS) strategy, we achieve a maximum network size of 150x10 and a peak working frequency of 100 MHz for the BCPNN-based associative memory system on the Xilinx Alveo U200 Card. The tradeoff between performance and hardware overhead of the design is explored and evaluated. Compared with the GPU counterpart, the FPGA-based implementation demonstrates significant improvements in both performance and energy efficiency, achieving a maximum latency reduction of 33.25x, and a power reduction of over 6.9x, all while maintaining the same network configuration., QC 20240513Part of ISBN 979-8-3503-9354-5

Evaluating the computational accuracy of Spiking Neural Network (SNN) implemented as in-situ learning on large-scale memristor crossbars remains a challenge due to the lack of a versatile model for the variations in non-ideal memristors. This brief proposes a novel behavioral variation model along with a four-stage pipeline for physical memristors. The proposed variation model combines both absolute and relative variations. Therefore, it can better characterize different memristor cycle-to-cycle (C2C) variations in practice. The proposed variation model has been used to simulate the behavior of two physical memristors. Adopting the non-ideal memristor model, the trace-based spiking-timing dependent plasticity (STDP) unsupervised in-memristor learning system is simulated. Although the synaptic-level weight simulation shows a performance degradation of 7.99% and 4.07% increase in the relative root mean square error (RRMSE), the network-level simulation results show no accuracy loss on the MNIST benchmark. Furthermore, the impacts of absolute and relative C2C variations on network performance are simulated and analyzed through two sets of univariate experiments., QC 20240412

Pathogenic bacteria significantly threaten human health, highlighting the need for precise and efficient methods for swiftly identifying bacterial species. This paper addresses the challenges associated with performing genomics computations for pathogen identification on embedded systems with limited computational power. We propose an optimized implementation of Self-Organizing Maps (SOMs) targeting a parallel ultra-low-power platform based on the RISC-V instruction set architecture. We propose two mapping methods for implementing the SOM algorithm on a parallel cluster, coupled with software techniques to improve the throughput. Orthogonally to parallelization, we investigate the impact of smaller-than-32-bit floating-point formats (smallFloats) on energy savings, precision, and performance. Our experimental results show that all smallFloat formats exhibit a 100% classification accuracy. The parallel variants achieve a speed-up of 1.98 × , 3.79 ×, and 6.83 × on 2, 4, and 8 cores, respectively. Comparing our design with a 16-bit fixed-point implementation on a coarse grain reconfigurable architecture (CGRA), the FP8 implementation achieves, on average, 1. 42 × energy efficiency, 1. 51 × speedup, and a 50% reduction in memory footprint compared to CGRA. Furthermore, FP8 vectorization increases the average speed-up by 2.5 ×., Part of proceedings ISBN: 979-835032649-9QC 20240212

The memristor has been extensively used to facilitate the synaptic online learning of brain-inspired spiking neural networks (SNNs). However, the current memristor-based work can not support the widely used yet sophisticated trace-based learning rules, including the trace-based Spike-Timing-Dependent Plasticity (STDP) and the Bayesian Confidence Propagation Neural Network (BCPNN) learning rules. This paper proposes a learning engine to implement trace-based online learning, consisting of memristor-based blocks and analog computing blocks. The memristor is used to mimic the synaptic trace dynamics by exploiting the nonlinear physical property of the device. The analog computing blocks are used for the addition, multiplication, logarithmic and integral operations. By organizing these building blocks, a reconfigurable learning engine is architected and realized to simulate the STDP and BCPNN online learning rules, using memristors and 180 nm analog CMOS technology. The results show that the proposed learning engine can achieve energy consumption of 10.61 pJ and 51.49 pJ per synaptic update for the STDP and BCPNN learning rules, respectively, with a 147.03× and 93.61× reduction compared to the 180 nm ASIC counterparts, and also a 9.39× and 5.63× reduction compared to the 40 nm ASIC counterparts. Compared with the state-of-the-art work of Loihi and eBrainII, the learning engine can reduce the energy per synaptic update by 11.31× and 13.13× for trace-based STDP and BCPNN learning rules, respectively., QC 20240703

Optoelectronic memristors are suitable candidates for hardware implementation of optical synapses in spiking neural networks (SNNs), thanks to their electrical and optical characteristics. To study the feasibility of memristor-based optical synapses in SNNs, a behavior model for optoelectronic memristors is proposed in this paper, including electrical programming modeling and photocurrent read modeling. Based on the model, the behavior of a molecular ferroelectric (MF)/semiconductor interfacial memristor is simulated. This paper also proposes an optical synaptic circuit for trace-based spike-timing-dependent plasticity (STDP) learning rule. The electrical characteristics of the memristor are explored and exploited to emulate the trace in the pairwise nearest-neighbor STDP, while the optical characteristics are utilized for non-destructive readout and weight calculation. Synaptic-level simulation results show a 99.96% correlation coefficient (CC) and a 1.91% relative root mean square error (RRMSE) in the weight approximate computation. Extending the simulation to the network level, the optoelectronic memristor-based unsupervised STDP learning system can achieve a 92.07± 0.64% accuracy on the MNIST benchmark., Part of ISBN 9798350300246QC 20230920

Fast-Fourier Transform is an important algorithm which is used in digital signal processing and communication applications. Furthermore, mixed-radix FFT provides flexibility and increases the speed of FFT computation. For real-time processing, efficient hardware implementation using reconfigurable architectures is preferred which can offer higher performance and flexibility. In this paper, we propose an architecture for the implementation of the FFT that is derived from the Dynamically Reconfigurable Resource Array and has multiple parallel processing cells while also providing the flexibility to select the radix for each stage of the FFT. The twiddle factor generator proposed in this architecture minimizes the memory requirements and simplifies the hardware. Using the proposed architecture, various length FFTs were mapped onto either single cell or multiple cells in parallel. It is observed that the proposed architecture improves the performance by 2x times when compared to the existing FFT architectures., QC 20230621

Computers have become essential to everyday life as much as electricity, communications and transport. That is evident from the amount of electricity we spend to power our computing systems. According to some reports it is estimated to be ≈ 7% of the total consumption worldwide. This trend is very worrisome, and the development of computing systems with lower power consumption is essential. This is even more important for battery-powered computers deployed in the field. The industry and the scientific community have realised that general-purpose computing platforms cannot offer that level of computational efficiency and that customisation is the solution to this problem. Application-Specific Integrated Circuits (ASICs) provide the highest efficiency in the mainstream implementation styles. ASICs have been shown to provide 100 to 1000× better computational efficiency than general-purpose computing platforms. However, the design cost of ASICs restricts it to products that have a large volume or large profit. In essence, to achieve ASIC-like computational efficiency, the design efficiency becomes the bottleneck. SynchorosVLSI design has been proposed to non-incrementally lower the design cost of custom ASIC-like solutions. The synchoros VLSI design is a novel concept that can reduce the design cost of ASICs and their manufacturing. Insynchoros design, the space is discretised, and the final design emerges by the abutment of synchoros micro-architecture level design objects called SiLago(Silicon Lego) blocks. The SiLago framework has the potential to reduce the design cost of ASICs and their manufacturing. This thesis makes three research areas of contributions toward synchoros VLSI design. The first area concerns composition by abutment. In this contribution, a design has been proposed to show how a clock tree can be created by abutting fragments inside the SiLago blocks. Additionally, the clock tree created by abutment was validated by the EDA tools and its cost metri, Datorer har blivit lika oumbärliga för vardagen som el, kommunikations- och transportmedel. Något som bekräftas av mängden el vi lägger på våra datorer. Några rapporter uppskattas mängden till hela ≈ 7 % av världens totala elbehov. Utvecklingen är mycket oroväckande och det är av högsta vikt att vi tar fram energisnålare datorer. Det är ännu viktigare för batteridrivna datorer. Både i näringslivet och i forskningsvärlden har man insett att standardiserade datorer och plattformar inte kan erbjuda samma prestanda och energisnålhet som datasystem specialbyggda för specifika ändamål kan. Appli-kationsspecifica integrerade kretsar (Application-Specific Integrated Circuit –ASIC) är det som oftast används när målet är högsta prestanda. Dessa har visats kunna uppnå 100 till 1000 gånger högre prestanda än standardiserade datasystem. Nackdelen med ASIC:er är att utvecklingskostnaderna är mycket höga och att de därför endast kan användas till produkter som massproduceras eller som har hög vinstmarginal. Utvecklingskostnaderna har alltså blivit flaskhalsen och det främsta hindret på vägen mot ASIC-liknande prestanda. För att komma runt flaskhalsen och drastiskt minska utvecklingskostnaderna för ASIC-liknande kretsar så har designmetoden synkoros storskalig integration (Synchorous Very Large-Scale Integration, VLSI) föreslagits. Synkoros VLSI är ett nytt koncept som kan minska ASIC:ers utvecklings- och produktionskostnader. Metoden går ut på att diskretisera utrymme så att designen uppkommer genom att mindre, sykorosa, SiLago-komponenter (Silicon Le-go) fogas samman. Potentiellt kan SiLago och dess ramverk minska ASIC:ers utvecklings- och produktionskostnader. Denna tes bidrar till tre forsknings-områden inom synkoros VLSI. Det första området handlar om design via sam-manfogning. Här föreslås en design av ett klockträd som skapas genom sam-manfogning av SiLago-komponenter. Klockträdet verifieras med elektronik-designverktyg (Electronic Design Automation, EDA) och prestandan jämf, QC 20220506

With the growing demand for more efficient hardware accelerators for streaming applications, a novel Coarse-Grained Reconfigurable Architecture (CGRA) that uses a DistributedTwo-Level Control (D2LC) system has been proposed in the literature. Even though the highly distributed and parallel structure makes it fast and energy-efficient, the single-issue instruction channel between the level-1 and level-2 controller in each D2LC cell becomes the bottleneck of its performance. In this paper, we improve its design to mimic a multi-issued architecture by inserting shadow instruction buffers between the level-1 and level-2 controllers. Together with a zero-overhead hardware loop, the improved D2LC architecture can enable efficient overlap between loop iterations. We also propose a complete constraint programming based instruction scheduling algorithm to support the above hardware features. The experiment result shows that the improved D2LC architecture can achieve up to 25% of reduction on the instruction execution cycles and 35% reduction on the energy-delay product., Part of proceedings: ISBN 978-3-9819263-6-1QC 20220503QC 20220121

State-of-the-art modern microprocessor and domain-specific accelerator designs are dominated by data-paths composed of regular structures, also known as bit-slices. Random logic placement and routing techniques may not result in an optimal layout for these data-path-dominated designs. As a result, implementation tools such as Cadence's Innovus include a Structured Data-Path (SDP) feature that allows data-path placement to be completely customized by constraining the placement engine. A relative placement file is used to provide these constraints to the tool. However, the tool neither extracts nor automatically places the regular data-path structures. In other words, the relative placement file is not automatically generated. In this paper, we propose a semi-automated method for extracting bit-slices from the Innovus SDP flow. It has been demonstrated that the proposed method results in 17% less density or use for a pixel buffer design. At the same time, the other performance metrics are unchanged when compared to the traditional place and route flow., QC 20221011

The Bayesian Confidence Propagation Neural Network (BCPNN) is a spiking model of the cortex. The synaptic weights of BCPNN are organized as matrices. They require substantial synaptic storage and a large bandwidth to it. The algorithm requires a dual access pattern to these matrices, both row-wise and column-wise, to access its synaptic weights. In this work, we exploit an algorithmic optimization that eliminates the column-wise accesses. The new computation model approximates the post-synaptic spikes computation with the use of a predictor. We have adopted this approximate computational model to improve upon the previously reported ASIC implementation, called eBrainII. We also present the error analysis of the approximation to show that it is negligible. The reduction in storage and bandwidth to the synaptic storage results in a 48% reduction in energy compared to eBrainII. The reported approximation method also applies to other neural network models based on a Hebbian learning rule., Part of proceedings ISBN: 978-3-9819263-5-4QC 20220413

Synchoros VLSI design style has been proposed as an alternative to the standard cell-based design style; the word synchoros is derived from the Greek word choros for space. Synchoricity discretises space with a virtual grid, the way synchronicity discretises time with clock ticks. SiLago (Silicon Lego) blocks are atomic synchoros building blocks like Lego bricks. SiLago blocks absorb all metal layer details, i.e., all wires, to enable composition by abutment of valid; valid in the sense of being technology design rules compliant, timing clean and OCV ruggedized. Effectively, composition by abutment eliminates logic and physical synthesis for the end user. Like Lego system, synchoricity does need a finite number of SiLago block types to cater to different types of designs. Global NoCs are important system level design components. In this paper, we show, how with a small library of SiLago blocks for global NoCs, it is possible to automatically synthesize arbitrary global NoCs of different types, dimensions, and topology. The synthesized global NoCs are not only valid VLSI designs, but their cost metrics (area, latency, and energy) are known with post-layout accuracy in linear time. We argue that this is essential to be able to do chip-level design space exploration. We show how the abstract timing model of such global NoC SiLago blocks can be built and used to analyse the timing of global NoC links with post layout accuracy and in linear time. We validate this claim by subjecting the same VLSI designs of global NoC to commercial EDA's static timing analysis and show that the abstract timing analysis enabled by synchoros VLSI design gives the same results as the commercial EDA tools., QC 20220323Part of proceedings: ISBN 978-1-4503-9083-5

This paper proposes a concise window function to build a memristor model, simulating the widely-observed non-linear dopant drift phenomenon of the memristor. Exploiting the non-linearity, the memristor model is applied to the in-situ neuromorphic solution for a cortex-inspired spiking neural network (SNN), spike-based Bayesian Confidence Propagation Neural Network (BCPNN). The improved memristor model utilizing the proposed window function is able to retain the boundary effect and resolve the boundary lock and inflexibility problem, while it is simple in form that can facilitate large-scale neuromorphic model simulation. Compared with the state-of-the-art general memristor model, the proposed memristor model can achieve a 5.8x reduction of simulation time at a competitive fitting level in cortex-comparable large-scale software simulation. The evaluation results show an explicit similarity between the non-linear dopant drift phenomenon of the memristor and the BCPNN learning rule, and the memristor model is able to emulate the key traces of BCPNN with a correlation coefficient over 0.99., Part of ISBN 978-1-6654-1913-0QC 20220216

The Bayesian Confidence Propagation Neural Network (BCPNN) has been implemented in a way that allows mapping to neural and synaptic processes in the human cortexandhas been used extensively in detailed spiking models of cortical associative memory function and recently also for machine learning applications. In conventional digital implementations of BCPNN, the von Neumann bottleneck is a major challenge with synaptic storage and access to it as the dominant cost. The memristor is a non-volatile device ideal for artificial synapses that fuses computation and storage and thus fundamentally overcomes the von Neumann bottleneck. While the implementation of other neural networks like Spiking Neural Network (SNN) and even Convolutional Neural Network (CNN) on memristor has been studied, the implementation of BCPNN has not. In this paper, the BCPNN learning rule is mapped to a memristor model and implemented with a memristor-based architecture. The implementation of the BCPNN learning rule is a mixed-signal design with the main computation and storage happening in the analog domain. In particular, the nonlinear dopant drift phenomenon of the memristor is exploited to simulate the exponential decay of the synaptic state variables in the BCPNN learning rule. The consistency between the memristor-based solution and the BCPNN learning rule is simulated and verified in Matlab, with a correlation coefficient as high as 0.99. The analog circuit is designed and implemented in the SPICE simulation environment, demonstrating a good emulation effect for the BCPNN learning rule with a correlation coefficient as high as 0.98. This work focuses on demonstrating the feasibility of mapping the BCPNN learning rule to in-circuit computation in memristor. The feasibility of the memristor-based implementation is evaluated and validated in the paper, to pave the way for a more efficient BCPNN implementation, toward a real-time brain emulation engine., QC 20220125

The increased demand for energy-efficient solutions compels system architects to explore the opportunities for minimizing area and power in the critical parts of a system. The register file is one such essential and critical component of any processor system that provides local storage for computing hardware such as arithmetic and logical unit. In this paper, we present an optimized design and implementation of a synthesizable register file that reduces the area and power consumption over an existing design. The proposed design is functionally equivalent to the existing design and uses latches in its core as main storage elements as opposed to the flip-flops; thus, reducing the area and power consumption. The proposed design has 10% less area and 23% less leakage power than the existing design when synthesized using a CMOS 45nm process libraries. Furthermore, the back-end implementation results show that the proposed design has 13% less core utilization and 2.3X less power., Part of proceedings: ISBN 978-1-6654-1992-5 QC 20220608

Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. Standard-cells are replaced by synchoros, large grain, VLSI design objects called SiLago (Silicon Lego) blocks. This new design style eliminates the need to synthesise ad hoc wires of any type: functional and infrastructural. SiLago blocks are organised into region instances. In a region instance, communication among SiLago blocks is synchronous and happens over a regional network on chip (NoC) whose fragments are also absorbed into SiLago blocks. Consequently, the regional NoCs get created by the abutment of SiLago blocks. The clock tree that is used in a region is called regional clock tree (RCT). The synchoros VLSI design style requires that the RCT, like the regional NoCs, is created by abutting its fragments. The RCT fragments are absorbed within the SiLago blocks. The RCT created by abutment is not an ad-hoc clock tree but a structured and predictable design with known cost metrics. The design of such an RCT is the focus of this paper. The scheme is scalable, and we demonstrate that the proposed RCT can be generated for valid VLSI designs of ~1.5 million gates. The RCT created by abutment is correct by construction, and its properties are predictable. We have validated the generated RCTs with static timing analysis to validate the correct-by-construction claim. Finally, we show that the cost metrics of the SiLago RCT is comparable to the one generated by commercial EDA tools., Part of proceedings: ISBN 978-1-6654-0713-7, QC 20230117

The Artificial Neural Networks (ANNs), like CNN/DNN and LSTM, are not biologically plausible. Despite their initial success, they cannot attain the cognitive capabilities enabled by the dynamic hierarchical associative memory systems of biological brains. The biologically plausible spiking brain models, e.g., cortex, basal ganglia, and amygdala, have a greater potential to achieve biological brain like cognitive capabilities. Bayesian Confidence Propagation Neural Network (BCPNN) is a biologically plausible spiking model of the cortex. A human-scale model of BCPNN in real-time requires 162 TFlop/s, 50 TBs of synaptic weight storage to be accessed with a bandwidth of 200 TBs. The spiking bandwidth is relatively modest at 250 GBs/s. A hand-optimized implementation of rodent scale BCPNN has been done on Tesla K80 GPUs require 3 kWs, we extrapolate from that a human scale network will require 3 MWs. These power numbers rule out such implementations for field deployment as cognition engines in embedded systems. The key innovation that this paper reports is that it is feasible and affordable to implement real-time BCPNN as a custom tiled application-specific integrated circuit (ASIC) in 28 nm technology with custom 3D DRAM - eBrainII - that consumes 3 kW for human scale and 12 watts for rodent scale. Such implementations eminently fulfill the demands for field deployment., QC 20210611

Simulation of large scale biologically plausible spiking neural networks, e.g., Bayesian Confidence Propagation Neural Network (BCPNN), usually requires high-performance supercomputers with dedicated accelerators, such as GPUs, FPGAs, or even Application-Specific Integrated Circuits (ASICs). Almost all of these computers are based on the von Neumann architecture that separates storage and computation. In all these solutions, memory access is the dominant cost even for highly customized computation and memory architecture, such as ASICs. In this paper, we propose an optimization technique that can make the BCPNN simulation memory access friendly by avoiding a dual-access pattern. The BCPNN synaptic traces and weights are organized as matrices accessed both row-wise and column-wise. Accessing data stored in DRAM with a dual-access pattern is extremely expensive. A post-synaptic history buffer and an approximation function thus are introduced to eliminate the troublesome column update. The error analysis combining theoretical analysis and experiments suggests that the probability of introducing intolerable errors by such optimization can be bounded to a very small number, which makes it almost negligible. Derivation and validation of such a bound is the core contribution of this paper. Experiments on a GPU platform shows that compared to the previously reported baseline simulation strategy, the proposed optimization technique reduces the storage requirement by 33%, the global memory access demand by more than 27% and DRAM access rate by more than 5%; the latency of updating synaptic traces decreases by roughly 50%. Compared with the other similar optimization technique reported in the literature, our method clearly shows considerably better results. Although the BCPNN is used as the targeted neural network model, the proposed optimization method can be applied to other artificial neural network models based on a Hebbian learning rule., QC 20210527

Cellular Automata (CAs), a ubiquitous computational tool proposed by John von Neumann, illustrate how great complexity emerges from simple rules of dynamical transitions between space and time interconnected simplistic entities. CAs perform as mathematical computation models, but also they are a powerful medium to model nature and natural systems. As a computational platform, CAs come with unified memory and computation in the same physical area, attributed as a strong candidate against the limitations of data transfer, known as the von Neumann bottleneck. On the other hand, Memristors with their inherent Computing-In-Memory compatibility, can be easily considered as appropriate nanoelectronic devices to be coupled with CAs towards an energy and time efficient computational paradigm. In particular, CA present a vast area of applications, comprising various NP-complete hard to be solved problems arriving from computer science field, like the well-known Shortest Path, Bin Packing, Knapsack and Max-clique problems, as well as physical, chemical and biological processes and phenomena, such as epileptic seizures in relation with healthy and pathogenic brain regions and, moreover, real life applications like pseudorandom number generation and simplistic, but with highly complex behavior, models like the famous Game of Life. The outcome of employing Memristors in CAs applications is promising in terms of parallelization, power consumption, scalability, reconfigurability, and high computing performance., QC 20230921