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We report a novel noise analysis for the leakage current during time-dependent dielectric degradation under bias stress, illustrated using AlGaN/GaN superlattice castellated field-effect transistors (SLCFETs). Gate step stress is a standard approach to test the robustness of the gate dielectric in OFF-state conditions. Here, by removing the background step transients measured using a standard parameter analyzer, the algorithm gives a quantitative value for the nonstationary superimposed noise in the dielectric leakage current during the test. Extraction of the power spectrum using windowing and a direct fit to the noise statistical distribution gives the noise magnitude. Although the technique allows the monitoring of noise increase during stress, it is shown that this is insufficient to clearly identify irreversible degradation in these devices. An additional low bias noise test between each step-stress bias has been used to detect the onset of permanent localized breakdown. This is manifested as both a change in noise magnitude and frequency dependence, occurring before it can be seen in leakage current or direct noise measurements.

In this article, we investigate the impact of hard-switching on the dynamic ON-resistance ( ${R}_{ \mathrm{ ON}}$ ) in the AlGaN/GaN high-electron mobility transistors (HEMTs). The pulsed measurements were taken on a set of GaN-on-Si wafers, showing a significant ${R}_{ \mathrm{ ON}}$ increase after hard-switching compared with soft-switching. The impact of hard-switching was found to be strongly dependent on the surface passivation stoichiometry. Both hot electrons and self-heating are generated during hard-switching and they were investigated separately. For the self-heating effect, we found that the heating energy dissipated during hard-switching followed a different trend to the dynamic ${R}_{ \mathrm{ ON}}$ , showing that self-heating was not responsible for the dynamic ${R}_{ \mathrm{ ON}}$ . Following hard-switching, we found that the recovery of the ${R}_{ \mathrm{ ON}}$ occurred on a time scale of microseconds, far too fast to be explained by buffer trapping. Consequently, we suggest that the hard-switching-induced hot electrons are trapped on the surface and result in the dynamic ${R}_{ \mathrm{ ON}}$ . To support these conclusions, we undertook 2-D-TCAD simulations. Self-heating was found to be incompatible with the measurements, and surface-trapped hot electrons during hard-switching were shown to be consistent with the experimental observation. Based on the analysis, we find that modifying the field plates and stoichiometries of SiN x can be the possible solutions to suppress dynamic ${R}_{ \mathrm{ ON}}$ after hard-switching.

$\beta $ -Ga2O3 is an attractive material for high-voltage applications and has the potential for monolithically integrated RF devices. A combination of Raman nano-particle thermometry measurement and thermal simulation has been used to measure the peak channel temperature due to self-heating in $\beta $ -Ga2O3 MOSFETs. The peak channel thermal resistance measured at the gate surface in the device center was $88~mm\,\! \cdot \, K/W$ . This value is higher than what has been previously reported using electrical methods, which determine an average temperature over the whole device area. Experimentally validated thermal simulations have been used to propose possible thermal management mitigation approaches.

In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility transistors which occurs in ON-state operation (V DS = 40 V, V GS = 0 V, I DS = 0.18 A mm−1). By analysing the dynamic ON-resistance (R ON) after OFF-state and ON-state stress in devices with different SiN x passivation stoichiometries, we find that this charge trapping can be largely suppressed by a high Si concentration passivation. Both potential probe and electroluminescence (EL) measurements further confirm that the stress can induce negative charge trapping in the gate–drain access region. It is shown that EL is generated as expected under the field plates at the gate edge, but is obscured by the field plates and is actually emitted from the device near the drain edge; hence care is required when using EL alone as a guide to the location of the high field region in the device. From temperature-dependent dynamic R ON transient measurements, we determine that the apparent activation energy of the measured ‘trap’ response is around 0.48 eV, and infer that they are located in the heavily carbon-doped GaN layer. Using the leaky dielectric model, we explain the response in terms of the hopping transport from the same substitutional carbon acceptor buffer dopants.

This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic ${R}_{ {\mathrm{\scriptscriptstyle ON}}}$ increase when they are submitted to soft switching up to ${V}_{{\text {DS}}}= 600$ V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic- ${R}_{ \mathrm{\scriptscriptstyle ON}})$ . The increase in dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice.

$\beta $ -Ga2O3 thin-channel MOSFETs were evaluated using both dc and pulsed ${I}$ – ${V}$ measurements. The reported pulsed ${I}$ – ${V}$ technique was used to study self-heating effects in the MOSFET channel. The device was analyzed over a large temperature range of 23 °C–200 °C. A relationship between dissipated power and channel temperature was established, and it was found that the MOSFET channel was heating up to 208 °C when dissipating 2.5 W/mm of power. The thermal resistance of the channel was found to be 73 °C-mm/W. The results are supported with the experimental Raman nanothermography and thermal simulations and are in reasonable agreement with pulsed ${I}$ – ${V}$ findings. The high thermal resistance underpins the importance of optimizing thermal management in future Ga2O3 devices.

Heat extraction from novel GaN/AlGaN superlattice castellated field effect transistors developed as an RF switch is studied. The device thermal resistance was determined as 19.1 ± 0.7 K/(W/mm) from a combination of Raman thermographymeasurements, and gate resistance thermometry. Finite element simulations were used to predict the peak temperatures and show that the three-dimensional gate structure aids the extraction of heat generated in the channel. The calculated heat flux in the castellations shows that the gate metal provides a high thermal conductivity path, bypassing the lower thermal conductivity superlattice, reducing channel temperatures by as much as 23%.

This paper reports an experimental demonstration of the time-dependent failure of GaN-on-Si power high-electron-mobility transistors with p-GaN gate, submitted to a forward gate stress. By means of combined dc, optical analysis, and 2-D simulations, we demonstrate the following original results: 1) when submitted to a positive voltage stress (in the range of 7–9 V), the transistors show a time-dependent failure, which leads to a sudden increase in the gate current; 2) the time-to-failure (TTF) is exponentially dependent on the stress voltage and Weibull-distributed; 3) the TTF depends on the initial gate leakage current, i.e., on the initial defectiveness of the devices; 4) during/after stress, the devices show a localized luminescence signal (hot spots); the spectral investigation mainly reveals a peak corresponding to yellow luminescence and a broadband related to bremsstrahlung radiation; and 5) 2-D simulations were carried out to clarify the origin of the degradation process. The results support the hypothesis that the electric field in the AlGaN has a negligible impact on the device failure; on the contrary, the electric field in the SiN and in the p-GaN gate can play an important role in favoring the failure, which is possibly due to a defect generation/percolation process.

This paper reports an analysis of the degradation mechanisms of GaN-based normally-off transistors submitted to off-state stress, forward-gate operation and electrostatic discharges. The analysis was carried out on transistors with p-type gate, rated for 600 V operation, developed within the European Project HIPOSWITCH. DC measurements, thermal analysis by transient interferometric mapping (TIM), and transmission line pulse (TLP) were used in combination to achieve a complete description of the degradation and failure processes. The results of this investigation indicate that: (i) the analyzed devices have a breakdown voltage (measured at 1 mA/mm) higher than 600 V; in off-state, drain current originates from gate–drain leakage for drain voltages (VDS) smaller than 500 V, and from vertical leakage through the conductive substrate for higher drain bias. (ii) step-stress experiments carried out in off-state conditions may induce instabilities in both drain–source conduction and gate leakage. Failure consists in the shortening of the gate junction, and occurs at VDS higher than 600 V. (iii) in forward bias, the p-type gate is stable up to 7 V; for higher gate voltages, a time-dependent degradation is detected, due to the high electric field across the AlGaN barrier; (iv) TIM analysis performed under short-circuited load conditions revealed hot spots at the drain side of the channel in the access region, thus indicating that these regions may behave as weak spots under high bias operation. Cumulative device degradation under such repeating pulses has also been revealed. (v) TLP tests were carried out to evaluate the voltage limits of the devices under off-state and on-state conditions. The results described within this paper provide relevant information on the reliability issues of state-of-the-art normally-off HEMTs with p-type gate.

Comparison between pulsed and CW large signal RF performance of field-plated $\beta $ -Ga2O3 MOSFETs has been reported. Reduced self-heating when pulse resulted in a power added efficiency of 12%, drain efficiency of 22.4%, output power density of 0.13 W/mm, and maximum gain up to 4.8 dB at 1 GHz for a 2- $\mu \text{m}$ gate length device. Increased power dissipation for higher ${V} _{\textsf {DS}}$ and ${I} _{\textsf {DS}}$ resulted in a degradation in performance, which, thermal simulation showed, could be entirely explained by self-heating. Buffer and surface trapping contributions have been evaluated using gate and drain lag measurements, showing minimal impact on device performance. These results suggest that $\beta $ -Ga2O3 is a good candidate for future RF applications.

This paper reports an investigation of the trapping mechanisms responsible for the temperature-dependent dynamic- $R_{\mathrm {\mathrm{{\scriptstyle ON}}}}$ of GaN-based metal–insulator–semiconductor (MIS) high electron mobility transistors (HEMTs). More specifically, we perform the following. First, we propose a novel testing approach, based on combined OFF-state bias, backgating investigation, and positive substrate operation, to separately investigate the buffer- and the surface-related trapping processes. Then, we demonstrate that the dynamic $R_{\mathrm {\mathrm{{\scriptstyle ON}}}}$ of GaN-based MIS-HEMTs significantly increases when the devices are operated at high temperature levels. We explain this effect by demonstrating that it is due to the increased injection of electrons from the substrate to the buffer (under backgating conditions) and from the gate to the surface (under positive substrate operation). Finally, we demonstrate that by optimizing the buffer and by reducing the vertical leakage, substrate-related trapping effects can be completely suppressed. The results described within this paper provide general guidelines for the evaluation of the origin of dynamic $R_{\mathrm {\mathrm{{\scriptstyle ON}}}}$ in GaN power HEMTs and point out the important role of the buffer leakage in favouring the trapping processes.

This paper reports on the trapping mechanism of GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs) designed to work in a cascode configuration. We defined a novel stress protocol (High Temperature, Source Current, HTSC) to investigate the degradation processes induced by semi-on state operation. We compare the results of HTSC with those obtained by the standard HTRB (high temperature reverse bias), with the aim of identifying different impact on the RON variation. While HTRB stress results in a strong negative bias/temperature instability (NBTI), under HTSC conditions no significant Vth shift is observed. This result is ascribed to the fact that under HTSC conditions the gate-source voltage difference is significantly smaller than under HTRB, thus having less impact on Vth stability. The technique described in this paper is useful to test the Vth stability of normally-on devices used in cascode configuration.

In order to assess the space compatibility of GaN-HEMT technology, radiation hardness tests are an essential requirement. In this field, Gallium Nitride exhibits excellent robustness with respect to radiation and GaN-based devices are providing very promising results for most of the typical space configurations. Nevertheless, in presence of very high fluence levels, displacement damage takes place reducing the device performances from the static to the dynamic point of view. This paper shows how the combination of radiation hardness tests and the improvement of deep level analysis allows us to quantify the DC and pulsed performance decrease induced by proton irradiation on a technology designed for space applications, highlighting some signatures useful for an early detection of the displacement damage. Results provide a consistent demonstration of (i) threshold voltage positive shift and (ii) trapping effect enhancement correlated with the proton irradiation fluences.

This paper describes a laboratory and methodology for the complete assessment of the reliability of microwave and power Gallium Nitride (GaN) devices. Examples related to deep level effects in GaN High Electron Mobility Transistors (HEMTs), to HEMT gate degradation and time dependent breakdown effects are described.

Reverse bias leakage in bulk GaN-on-GaN pn diodes has been studied as a function of time. A peak was observed in the current transient and attributed to impurity band conduction along dislocations which is modulated by the field effect of charged decorating clusters. This model is consistent with reports of vacancy clustering around dislocations during growth.

GaN devices are promising candidates for the next generation power devices for energy efficient applications. Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility ; (2) cost ; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices in their next generation products, proven device and product reliability is a must. Cost is kept acceptably low by growing the GaN epi stack on 6inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines, with a proper contamination control protocol in place. This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). The need to do reliability investigations based on statistical data on large area power transistors (100+ mm gate width) instead of small test structures will be emphasized. Acceleration models and statistical distribution models (Weibull, lognormal) are discussed. The correlation between the GaN buffer stack vertical leakage and the parametric drift in prime device parameters under accelerated stress will be highlighted. Furthermore, since the MOCVD epi layers of the GaN-on-Si buffer stack are key to the device performance, a measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, …) based on simple transmission line structures, is outlined. This information will also be linked to the so-called “dynamic Ron”, a recoverable reduction in on-state current due to the trapping of charges in the buffer stack and/or the interface. Finally, it will be shown that through proper engineering of the epi buffer stack, device layout and device passivation scheme, dynamic Ron-free power transistors can be obtained.

This paper presents a detailed study of the failure mechanisms induced by a forward bias overstress on gallium nitride (GaN) high electron mobility transistors (HEMTs) with p-type gate. DC measurements demonstrate that GaN-HEMTs with p-GaN gate show a time-dependent catastrophic degradation when submitted to forward-gate overstress. Time to failure (TTF) can be described by a Weibull distribution and has an exponential dependence on the stress voltage. The overstress induces an increase in the gate current well correlated to the electroluminescence (EL) signal. The origin of the degradation is discussed by means of 2D simulations, suggesting that the electric field in the AlGaN has a negligible influence in the failure process.

The aim of this work is to quantitatively investigate the physical origin of the temperature-dependent dynamic R on in GaN based power transistors grown on silicon substrate. The analysis is based on combined trapping/detrapping measurements. Trapping was induced by exposing the devices to two different bias points: off-state bias (V GS =−10 V, V DS =100 V, and V B =0 V), and backgating bias (V GS =0 V, V DS =0 V, and V B =−100 V). The experimental data collected within this paper demonstrate the following relevant results: (i) when submitted to high temperature levels, dynamic R on shows a significant increase; (ii) combined off-state stress and backgating tests suggest that trapping proceeds through the injection of electrons from the buffer towards traps located in the GaN, next to the channel region; (iii) the temperature-dependent dynamic R on can be significantly reduced through the optimization of the growth and fabrication process.

GaN HEMTs for high-frequency operation are now exhibiting outstanding results in both RF performances and long-term stability, but at the moment there is not a unique indication of which failure mechanism affects the device performances in long-time scale, nor a proved technique which allows to identify the best failure accelerating factor useful for a consistent life-time extraction. In this topic, the paper tries to point-out the efficacy of short-term tests on the investigation of failure modes on two generations of AlGaN/GaN 0.25 μm gate-length HEMT transistors, highlighting the failure signatures corresponding to the early appearance of the failure modes typical of this technology: (i) a first mode correlated with a limited performance degradation marked by a left threshold voltage shift, and (ii) a second much more degrading failure mode, associated with a right threshold voltage shift. As a result, this simple preliminary investigation gives a consistent evaluation of the really improved reliability behaviour of the new HEMT technology, which shows excellent robustness from high-field to extremely high-power bias conditions, pushing out the more damaging failure mechanism from the typical operating conditions.