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15. Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications

Author

Harald Bucher, Simon Reder, Panayiotis Alefragis, Steven Derrien, Peer Ulbig, David Mueller, Jürgen Becker, Christian Ferdinand, Oliver Oey, Timo Stripf, Clément David, Fabian Kempf, Umut Durak, Nikolaos S. Voros, Isabelle Puaut, Stefanos Skalistis, Karlsruhe Institute of Technology (KIT), Technological Educational Intitute of Western Greece (TWG), Technological Educational Institute of Western Greece [Patra] (TEI), Pushing Architecture and Compilation for Application Performance (PACAP), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN), Emmtrix Technologies, AbsInt GmbH (Angewandte Informatik), AbsInt, ESI Group (ESI Group), Deutsches Zentrum für Luft- und Raumfahrt [Braunschweig] (DLR), Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-CentraleSupélec-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), ARCHITECTURE (IRISA-D3), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Inria Rennes – Bretagne Atlantique, and Institut National de Recherche en Informatique et en Automatique (Inria)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], 0209 industrial biotechnology, Computer science, Aerospace Engineering, 02 engineering and technology, Parallel computing, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], computer.software_genre, 020901 industrial engineering & automation, 0203 mechanical engineering, Worst-case execution time, Model-based design, Avionics, Electrical and Electronic Engineering, Multi-core, Engineering & allied operations, 020301 aerospace & aeronautics, Multi-core processor, Architecture description language, Application programming interface, Parallelization, TAWS, Supercomputer, Computer Science Applications, [INFO.INFO-PF]Computer Science [cs]/Performance [cs.PF], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Compiler, ddc:620, computer
Abstract

International audience; Multicore processing systems are the solution of choice to provide high embedded computing performance, but drawbacks in timing predictability and programmability limit their adoption in safety-critical aerospace applications. This work presents a compiler tool flow for automated parallelization of model-based real-time software, which addresses the shortcomings of multicore architectures in real-time systems. The flow is demonstrated using a model-based terrain awareness and warning systems (TAWSs) and an edge detection algorithm from the image-processing domain. Model-based applications are first transformed into real-time C code and, from there, into a well-predictable parallel C program. Tight bounds for the worst-case execution time (WCET) of the parallelized program can be determined using an integrated multicore WCET analysis. Thanks to the use of an architecture description language, the general approach is applicable to a wider range of target platforms. An experimental evaluation for a research architecture with network-on-chip interconnect shows that the parallel WCET of the TAWS application can be improved by a factor of 1.77 using the presented compiler tools.

Published
2019
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16. Dynamic Interference-Sensitive Run-time Adaptation of Time-Triggered Schedules

Author

Stefanos Skalistis and Angeliki Kritikakou, Skalistis, Stefanos, Kritikakou, Angeliki, Stefanos Skalistis and Angeliki Kritikakou, Skalistis, Stefanos, and Kritikakou, Angeliki

Abstract

Over-approximated Worst-Case Execution Time (WCET) estimations for multi-cores lead to safe, but over-provisioned, systems and underutilized cores. To reduce WCET pessimism, interference-sensitive WCET (isWCET) estimations are used. Although they provide tighter WCET bounds, they are valid only for a specific schedule solution. Existing approaches have to maintain this isWCET schedule solution at run-time, via time-triggered execution, in order to be safe. Hence, any earlier execution of tasks, enabled by adapting the isWCET schedule solution, is not possible. In this paper, we present a dynamic approach that safely adapts isWCET schedules during execution, by relaxing or completely removing isWCET schedule dependencies, depending on the progress of each core. In this way, an earlier task execution is enabled, creating time slack that can be used by safety-critical and mixed-criticality systems to provide higher Quality-of-Services or execute other best-effort applications. The Response-Time Analysis (RTA) of the proposed approach is presented, showing that although the approach is dynamic, it is fully predictable with bounded WCET. To support our contribution, we evaluate the behavior and the scalability of the proposed approach for different application types and execution configurations on the 8-core Texas Instruments TMS320C6678 platform, obtaining significant performance improvements compared to static approaches.

Published
2020
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17. Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures

Author

Benjamin Rouxel and Stefanos Skalistis and Steven Derrien and Isabelle Puaut, Rouxel, Benjamin, Skalistis, Stefanos, Derrien, Steven, Puaut, Isabelle, Benjamin Rouxel and Stefanos Skalistis and Steven Derrien and Isabelle Puaut, Rouxel, Benjamin, Skalistis, Stefanos, Derrien, Steven, and Puaut, Isabelle

Abstract

Multi-core systems using ScratchPad Memories (SPMs) are attractive architectures for executing time-critical embedded applications, because they provide both predictability and performance. In this paper, we propose a scheduling technique that jointly selects SPM contents off-line, in such a way that the cost of SPM loading/unloading is hidden. Communications are fragmented to augment hiding possibilities. Experimental results show the effectiveness of the proposed technique on streaming applications and synthetic task-graphs. The overlapping of communications with computations allows the length of generated schedules to be reduced by 4% on average on streaming applications, with a maximum of 16%, and by 8% on average for synthetic task graphs. We further show on a case study that generated schedules can be implemented with low overhead on a predictable multi-core architecture (Kalray MPPA).

Published
2019
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18. Modeling of Reconfigurable Medical Ultrasonic Applications in BIP

Author

Stefanos Skalistis and Alena Simalatsar, Skalistis, Stefanos, Simalatsar, Alena, Stefanos Skalistis and Alena Simalatsar, Skalistis, Stefanos, and Simalatsar, Alena

Abstract

Medical ultrasonic imaging applications require high quality of images produced in real-time often with limited resources available. Deadlock-freedom and confluency must be guaranteed to ensure the correctness of the applications, while feasibility and optimality properties are required to provide the best Quality of Service (QoS) within available resources. In this paper we introduce BIP (Behavior-Interaction-Priority) framework components as main building blocks to model such applications in a correct-by-construction manner. Based on those components we model a reconfigurable multi-mode processing pipeline for ultrasonic imaging that supports QoS management by topology reconfiguration. Finally, as a proof of concept, we present a simple quality controller as a well-triggered component, which when combined with the processing pipeline can manipulate the quality of image processing.

Published
2014
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19. Safe and Efficient Deployment of Data-Parallelisable Applications on Many-Core Platforms: Theory and Practice

Author

Stefanos Skalistis, Giovanni De Micheli, Federico Angiolini, and Alena Simalatsar

Subjects
010302 applied physics, Parallelizable manifold, estimation, Computer science, delays, Distributed computing, interference, Computational modeling, 02 engineering and technology, Interference (wave propagation), runtime, 01 natural sciences, 020202 computer hardware & architecture, Data modeling, data models, Many core, Hardware and Architecture, Software deployment, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Adaptation (computer science), Software
Abstract

The safe and, at the same time, efficient deployment of parallelisable applications on many-core platforms is a challenging task. Theoretical Models of Computation (MoC) require the realistic estimation of task Worst-Case Execution Time (WCET) to provide safe latency guarantees. Due to interferences on shared resources, task WCET estimations are often exceedingly pessimistic. In reality, though, rarely do all the tasks execute with their WCET, thus introducing an efficiency gap, which is of consequence in realizing safety-critical and mixed-criticality systems. In this paper, we outline the additional research efforts required to i) derive a safe deployment from a MoC reducing that efficiency gap and ii) adapt at runtime to further improve performance and still preserve safety. We also outline the impact of the level of data-parallelisation onto this efficiency gap and present experimental evidence of the performance improvements from accurate WCET estimation, level of data-parallelisation and runtime adaptation.

20. Worst-case execution time analysis for many-core architectures with NoC

Author

Stefanos Skalistis and Alena Simalatsar

Subjects
010302 applied physics, Computer science, Distributed computing, Task mapping, Optimal deployment, 02 engineering and technology, Parallel computing, 01 natural sciences, Execution time, 020202 computer hardware & architecture, Scheduling (computing), Memory bank, Many core, Worst-case execution time, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering
Abstract

The optimal deployment of data streaming applications onto multi-/many-core platforms providing real-time guarantees requires to solve the application partitioning/placement, buffer allocation, task mapping and scheduling optimisation problem using the tasks Worst-Case Execution Time (WCET). In turn, task WCET varies due to interferences that tasks experience when accessing shared resources, which vary depending on the solutions of the optimisation problem. To break this cyclic dependency we propose a detailed interference-based method that first over-approximates WCET based on the solution for application partitioning/placement and then tightens it by pruning out the interferences from tasks not overlapping in memory access and time. We prove that the derived bounds are safe. We have found that interferences on average amount to 10 % of WCET, and were able to improve the latency-guarantee up to 34 %.

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