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Active cell balancing is the process of equalizing the State-of-Charge (SoC) of all cells in a series-connected battery pack via charge transfers. While several balancing architectures and equalization strategies exist in the literature, optimization of the circuit components in a balancing architecture has not been sufficiently studied so far. Intuitively, one would select components with low parasitic resistances to minimize the energy dissipation. However, as will be shown in this paper, this might not be an optimal choice in most situations. In this paper, we propose an optimization framework that performs an efficient design space exploration to identify the energy-efficient circuit configuration of a balancing architecture. Moreover, for the first time, we propose a methodology to obtain the optimal operating frequency of an active cell balancing architecture and a control circuit to maintain the operation at the optimal frequency. For this purpose, we derive a closed-form analytical model of the charge transfer process with which we obtain the performance metrics required for our framework. Case studies show that such optimally dimensioned active cell balancing architectures operated at the optimal frequency reduce the energy dissipation by approximately 49% compared to the intuitive approach of selecting components with least parasitic resistances. [ABSTRACT FROM AUTHOR]

With the rapid expansion of IoT devices and their applications, there is an increasing demand for efficient and secure authentication mechanisms to protect against unauthorized access. Traditional authentication mechanisms face limitations regarding computational speed, communication costs, and vulnerability to cyber-attacks. Zero-knowledge proof (ZKP) protocols have emerged as an effective solution for achieving secure and efficient authentication in such environments without revealing sensitive information. Among ZKP protocols, Σ -protocols, a class of interactive ZKP protocols, have been employed for their efficiency and security. However, their interactive nature necessitates multiple rounds of communication, which can reduce efficiency and increase communication overhead for resource-constrained devices. Many works have aimed to eliminate the interaction of Σ -protocols by utilizing a transformation called the Fiat–Shamir transformation (FST). However, there is still a concern regarding the soundness of the FST as it can sometimes convert a secure Σ -protocol into an insecure non-interactive zero-knowledge (NIZK) authentication scheme. In this paper, we propose an approach for transforming Σ -protocols into a NIZK protocol based on the FST, yielding significant enhancements in efficiency, communication overhead reduction, and elimination of interaction. Our proposed protocol enables the completion of the authentication process in a single request while also strengthening the soundness of Σ -protocols in comparison with the traditional FST by requiring two authentication factors instead of one. To demonstrate our approach's robustness, we conducted comprehensive informal and formal security analyses (using the Tamarin-Prover). Our protocol demonstrated completeness, soundness, zero-knowledge properties, and robustness against attacks, including eavesdropping, message modification, replay, and brute force attacks. Additionally, our performance analysis displayed a remarkable 50% improvement in computational cost compared to traditional Σ -protocols, underscoring its efficiency for practical use. [ABSTRACT FROM AUTHOR]

Due to the growing interconnectedness and complexity of in-vehicle networks, in addition to safety, security is becoming an increasingly important topic in the automotive domain. In this paper, we study techniques for detecting security infringements in automotive electrical and electronic (E/E) architectures. Toward this we propose in-vehicle network traffic monitoring to detect increased transmission rates of manipulated message streams. Attacks causing timing violations can disrupt safety-critical functions and have severe consequences. To reduce costs and prevent single points of failure, our approach enables an automatic distribution of detection tasks among selected E/E architecture components, such as a subset of electronic control units. First, we analyze a concrete E/E system architecture to determine the communication parameters and properties necessary for detecting security attacks. These are then used for a parametrization of the corresponding detection algorithms and the distribution of attack detection tasks. We use a lightweight message monitoring method and optimize the placement of detection tasks to ensure a full-coverage of the E/E system architecture and a timely detection of an attack. [ABSTRACT FROM PUBLISHER]

Active cell balancing improves the performance of a battery pack by transferring charge from one cell to another. Associated design questions require multiple simulations with 100 cells over several hours. Since the most efficient transfer methods switch between phases in the kilohertz range, these simulations require high computational effort or reduced accuracy. To enable detailed analysis on a large scale, this paper includes state-of-the-art electrical battery models in active balancing simulation while keeping the computation effort for one transfer in the low millisecond range. This is achieved in three steps. First, we model the dynamics of each transfer phase using standard equivalent circuit abstraction. Next, we find closed form equations for the so-defined phase dynamics, yielding an iterative approach that saves computation time by replacing the numerical solver. Finally, we employ error control techniques to aggregate phases in that iteration, systematically reducing the millions of phase evaluations that would be necessary otherwise. Our experiments show that the speedup from equivalent circuit dynamics to error-controlled aggregation almost reaches five orders of magnitude while introducing virtually no additional error. This enables simulations of realistic balancing scenarios in less than a second and is hence suitable for design space exploration. [ABSTRACT FROM PUBLISHER]

Active balancing architectures effectively increase the efficiency of large battery packs by equalizing charge between cells. For this purpose, a balancing circuit and appropriate control scheme have to be designed to enable the charge transfer via energy storage elements such as inductors. Using a manual approach to design balancing architectures can be tedious and error-prone, resulting in potentially suboptimal solutions. As a remedy, this paper presents an automatic synthesis of balancing circuits and their corresponding control, optimizing the number of required metal-oxide-semiconductor field-effect transistors, and necessary control signals. The proposed synthesis combines a satisfiability solver to explore the search space with a graph-based verification that iteratively excludes infeasible solutions until the optimal architectures are obtained. The experimental results are carried out for three given template circuits and two signal templates. The synthesis results in architectures that are superior in terms of all design objectives in comparison to solutions from literature that result from a manual design approach. [ABSTRACT FROM PUBLISHER]

Car manufacturers provide a growing variety of models and configuration options for customers. In the highly competitive and cost-driven automotive industry, managing these variants and increasing the reuse of functionality in different variants has therefore become one of the key challenges. This paper addresses the problem of generating variant schedules for time-triggered electrical/electronic-architectures. We propose a multischedule synthesis approach that determines the common parts of multiple variants and generates a schedule that exploits this commonality. Hence, a multischedule defines individual variant schedules with an identical schedule for applications common to different variants. This makes these applications variant-independent, thus, reduces the testing and integration efforts as it only has to be done once. Multischedule synthesis involves several challenges, viz., identification of commonality between different variants, schedule synthesis for common parts, and the integration of uncommon parts. Consequently, the schedule synthesis approach presented here is very different from conventional approaches. Finally, to address the increased complexity, we also propose a divide-and-conquer approach to partition the problem, improving the scalability. [ABSTRACT FROM AUTHOR]

Modern vehicles employ a large amount of distributed computation and require the underlying communication scheme to provide high bandwidth and low latency. Existing communication protocols like Controller Area Network (CAN) and FlexRay do not provide the required bandwidth, paving the way for adoption of Ethernet as the next generation network backbone for in-vehicle systems. Ethernet would co-exist with safety-critical communication on legacy networks, providing a scalable platform for evolving vehicular systems. This requires a high-performance network gateway that can simultaneously handle high bandwidth, low latency, and isolation; features that are not achievable with traditional processor based gateway implementations. We present VEGa, a configurable vehicular Ethernet gateway architecture utilising a hybrid FPGA to closely couple software control on a processor with dedicated switching circuit on the reconfigurable fabric. The fabric implements isolated interface ports and an accelerated routing mechanism, which can be controlled and monitored from software. Further, reconfigurability enables the switching behaviour to be altered at run-time under software control, while the configurable architecture allows easy adaptation to different vehicular architectures using high-level parameter settings. We demonstrate the architecture on the Xilinx Zynq platform and evaluate the bandwidth, latency, and isolation using extensive tests in hardware. [ABSTRACT FROM AUTHOR]

During the last decade Electric Vehicles (EVs) surged in popularity. However, their mass adoption is slowed by the limited capacity of their Energy Storage System (ESS). Lithium Ion (Li-Ion) technology has established itself as the de-facto standard for mobile applications, though its energy density and cost put a hard limit on the maximum size of viable EV battery packs. Maximizing its utilization therefore becomes of central importance. To efficiently use a battery pack over its entire lifetime, the State of Health (SoH) of the cells needs to be taken into account. In this paper, we propose a novel preconditioning algorithm to minimize the time an EV is connected to the charging station. Our proposed approach uses existing Active Cell Balancing (ACB) hardware of the battery pack to precondition the State of Charge (SoC) of cells such that all cells reach the top SoC threshold at the same time without requiring an additional balancing phase during charging. This is done by considering the individual cells' SoH to precondition them for achieving an equal time to charge fully. Applying the same approach for discharging, we can extend the driving range of an EV, which otherwise is limited by the cell with the lowest SoC in the pack. Our analysis of various usage scenarios shows that our proposed preconditioning algorithm increases the usable energy of the battery pack by up to 1.8% compared to conventional balancing algorithms while effectively halving the time connected to a charging station, all without requiring any additional hardware components. [ABSTRACT FROM AUTHOR]