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In large-size flat panel display modules for TV applications, signaling channels designed on flexible printed circuit (FPC) cable or chip-on-film (COF) package are incomparably shorter than source PCBs, but they can play a significant role in determining overall signal integrity (SI) performance. This work analyzes interconnection designs on FPC cable and COF package in terms of impedance matching and crosstalk. It also provides channel design considerations and design guidelines for better SI performance in flexible channels on high-speed interface for large-size LCD TV applications.

In this work, we present the multiple high density capacitance options available to help achieve PDN target and go over the various aspects involved (modelling, system simulations and optimizations) to achieve a PI compliant HPC system PDN design

EMI (Electrical Magnetic Interference) regulation is strictly applied to display panel products, and it needs to be considered from IC design stage. In this work, we propose a virtual EMI simulation technique for TV products to simulate the EMI test of the CISPR 16 standard. The virtual EMI simulation implements both display panel and EMI measurement environment by Ansys HFSS simulation software, which enable to predict the EMI problem of the display panel products in IC design stage. The proposed simulation technique showed a good correlation with the EMI measurement results of the 55-inch 4K display model.

This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.

In this work, we present a comprehensive analysis methodology for parameters that should be considered in terms of power integrity (PI) and signal integrity (SI) when designing 3D IC. By analyzing the basic structure of the 3D IC, each block was separated and modified to a simplified model using equivalent circuit formula to create a simplified full system simulation environment. Using this setup, voltage noise in the system power delivery network (PDN) environment considering various through-silicon-via (TSV) types, pitch, etc. was analyzed, and the difference from the existing 2D structure was compared. In addition, it is found that there is a trade-off relationship between voltage drop and area overhead by the increase of number of TSVs and the optimization process that satisfies both conditions simultaneously. Finally, the IP power density that are required on the top and bottom dies was examined for the IP layout considering thermal effects in the initial design stage of 3D IC. Each of these individual analyses is summarized in a unified database and eventually is able to provide a design guideline at the early stage through the process of finding out a solution that satisfies all given conditions.

In this work, we introduce platform-level power integrity (PI) solutions to enable high-power core IPs and high-bandwidth memory (HBM) interface for HPC/AI applications. High-complexity design methodology becomes more significant to enable high-power operations of CPU/GPU/NPU that preforms iteratively tremendous computing processes. In order to achieve high-power performance at larger than 200W class, system-level PI analysis and design guide at early design stage is required to prevent drastic voltage variations at the bump under comprehensive environments including SoC, interposer, package and board characteristics. PI solutions based on high-density on-die capacitors are suitable for mitigating voltage fluctuations by supplying quickly stored charges to silicon devices. In adopting 2-/3-plate metal-insulator-metal (MIM) capacitor with approximately 20nF/mm2 and 40nF/mm2, and integrated stacked capacitor (ISC) with approximately 300nF/mm2, it is demonstrated that voltage properties (drop and ripple) are able to be improved by system-level design optimization such as power delivery network (PDN) design and RTL-architecture manipulation. Consequently, system-level PI solutions based on high-density capacitor are anticipated to contribute to improving target performance of high-power products in response to customer's expectation for HPC/AI applications.

In this work, we investigate power integrity (PI) effects of using metal-insulator-metal (MIM) capacitors for high power applications. As transistor density for integrated circuitry increases at advanced process nodes, the PI management of high power applications becomes more challenging. MIM capacitor offers a possible solution to overcome these issues by acting as a fast response charge tank. The MIM capacitor mentioned here was designed for high-power IP with about $2 mW/$um2 at 1GHz. Based on the simulation results, PI properties was analyzed by the designed MIM capacitor considering offchip parameters. As a result, it is demonstrated that the worst and the average of dynamic voltage drop (DVD) are improved by 22.5% and 42.5%, respectively when compared to the case without MIM capacitors. In addition, usage of MIM capacitors reduces the package decap requirement by 54% to meet same target voltage drop. Consequently, the usage of MIM capacitor is advantageous to make high power IP blocks stable in an integrated chip. Thus, it is expected to develop the design methodology of effective MIM usage and investigate system-level optimal capacitor configuration considering various decoupling capacitors such as on-die capacitor, MIM capacitor, and package decoupling capacitor.

In this work, we introduce a comprehensive methodology for the power integrity/signal integrity analysis of SoC and silicon-based interposers in a HPC platform. By conducting a comprehensive investigation of the global chip-level PDN impact by electrical interactions between the chip, package, and board in the system, an efficient power delivery network was designed to meet HPC specifications. This was achieved by extracting long-term test scenarios (microsecond-order duration) to estimate voltage drop at the bumps and deployment of decoupling capacitors considering the optimal placement and numbers within an allowable cost budget. This analysis also yielded the benefit of reduction in power domains/ball count/package layers which further reduced costs. In addition to the Power Integrity, signal properties were analyzed under the allowed channel conditions (channel width and spacing, shielding lane placement). As a result, the channel design parameters are found to meet the criteria of eye opening including power noise and crosstalk effects. It was demonstrated that the electrical properties of the HBM2e IP are successfully operational up to 3.2Gbps.

This paper presents a framework and runtime system, Amino, for developing and executing distributed applications in highly dynamic computing environment consisting of cloud resources, edge nodes and/or devices such as phones and smart cameras. This work is based on Sapphire [1] - a general-purpose distributed programming platform. In Sapphire, application objects (called Sapphire Objects) run inside kernel servers (KS), and Kernel server instance runs on every device or cloud node. Between Kernel Server and an application object is a layer called Deployment Manager (DM). Inbound and outbound communications to/from Sapphire objects will be intercepted and processed by deployment manager. Each DM provides one specific distributed system capabilities, e.g. caching, resource leasing, replication, data partitioning etc. Programmers selectively choose DMs to manage Sapphire objects. As part of this work (Amino), we re-implemented and extended Sapphire platform to support the invocation of methods on objects written in multiple languages and to support attaching multiple DMs to a Sapphire object for increased distribution capabilities. Finally, in the work, we introduce a code offloading design for dynamically moving application objects between devices and cloud servers at runtime to optimize a user specified objective, e.g. to reduce latency or to save energy consumption.

In this work, we propose an analytical approach for accurate estimation on on-die decoupling capacitance in the power delivery network (PDN) of an integrated chip (IC). This paper suggests a simplified model of PDN which avoids the complex mesh structures traditionally generated but still provides a good fit model with measurement. The suggested model consists of branched multiple cells in a chained node formation. By manipulating multiple variables accounting for a complex PDN structure, the curve fitting process was performed and the best-fitted curve was found to be valid with less than 3% error tolerance through the solution-search processes by comparing capacitor values in a known mesh structure. Consequently, complex matrix PDN can be simplified and converted to an analytical model through the proposed chained structure. This approach is expected to effectively validate the value of implemented decoupling capacitance in the PDN of a designed IC with conventional low-impedance measurement techniques.

Todays, the power optimization of a mobile product aims at designing more effective power/ground layout structure without performance degradation. Thus, it is necessary to optimize power/ground domains based on analyzing the performance of composing IPs between adjacent power domains. In this work, a design solution for power optimization based on CPS (chip-package-system) co-analysis was applied at a full chip scale using a mobile processor. A current noise model of merging IPs under operation scenarios was extracted and noise impact by merging the power domain of neighboring IPs was analyzed including package and board electrical properties. By simulation results using the proposed approach, the number of power domains can be reduced up to 32%. In order to verify the suggested approach, the performance of package assembled samples was measured and compared between merged and separate power domains. As a result, the validation of the applied analysis approach was successfully demonstrated by not measuring any performance degradation. In addition, we also applied a machine-learning technique for CPS co-analysis to effectively optimize a system-level PDN design. It was demonstrated to significantly reduce the number of possible combinations in a PDN configuration with a wide-range solution space. Consequently, the proposed design solution for power domain optimization is expected to be effectively applicable for maintaining the competitiveness of product development in various industry applications.

In this paper, an accurate noise level estimation technique in the design stage for LPDDR system is presented. In order to predict the system performance, the equivalent circuit based simulation model and the input parameter range for the sweep simulation is required. The package and board are modeled by using RLC equivalent circuits. The input parameter range is determined by investigating the characteristics of the existing products. The noise level of the LPDDR system in the mobile platform can be estimated by using equivalent circuit model and input parameters. It is shown that noise level at the input pad of the receiver using the proposed method has a good agreement with S-Parameter based model within less than 8dB.

In a magnetically aligned anisotropic conductive adhesive (MA-ACA), high-density vertical interconnects (VIs) are created by agglomerating micron-scale ferromagnetic particles in an epoxy medium through their magnetization process when a magnetic field is externally induced. In this paper, we characterize the radio-frequency properties of pad-to-pad transition created in an MA-ACA on small input and output (I/O) pads less than 100 × 100- μm. In order to analyze created VIs in an MA-ACA, an equivalent circuit model is suggested and validated by using a parasitic extraction approach from the measured S-parameter responses of a silicon-on-silicon test sample. In addition, the effects of the composing parasitics are investigated depending on vertical interconnect density (VID) by adjusting the weight fraction of loading conductive particles. Furthermore, based on a uniform-spacing distribution model of VIs, a failure rate of a pad-to-pad transition is estimated depending on I/O pad size. Experimentally, by refining loading conductive particles, the RF properties of a pad-to-pad transition on silicon test samples are demonstrated to be more consistent. Therefore, by characterizing the RF performance of a pad-to-pad transition depending on VID, a proposed RF packaging approach using an ACA is expected to be effectively applicable to high-density RF applications.

A self-assembly process in a magnetically aligned anisotropic conductive adhesive (MA-ACA) is a novel approach to selectively create high-density vertical interconnects by magnetic interaction between ferromagnetic input-output pads and particles. In order to characterize self-assembly vertical interconnects created in an MA-ACA, quad-flat no-lead chips with 40 daisy chain pads were assembled on a printed circuit board. In reliability tests, the dc resistance of self-assembly test samples was observed to be 35.9% and -12.1% changed at temperatures of 85°C and -55°C, respectively, after 700 thermal shock cycles and 0.4% changed after an 8-h vibration test. In contrast, the dc resistance was observed to be significantly 41.4 Ω increased due to humidity absorption after an 85°C temperature-85% humidity test for 500 h. Thus, in order to prevent humidity percolation in the self-assembly vertical interconnects, a Parylene-C material was used as a barrier layer. The dc resistance change of Parylene-deposited test samples with a thickness of 10 μm was observed to be greatly 85.2% reduced after an 85°C temperature-85% humidity test. In addition, based on a Weibull distribution model, the mean time to failure of self-assembly vertical interconnects was estimated to be importantly 94.7% improved. Consequently, the proposed self-assembly packaging using a Parylene material is applicable to cost-effective electronic applications.

An increase in electromagnetic interference (EMI) noise in mobile application directly affects the performance of the other chips or antenna that can lead to the degradation of total isotropic sensitivity (TIS) and system reliability. According to our near fiend scanning (NFS) results, electromagnetic (EM) noise emitted from AP-LPDDR memory interface in a package on package (POP) structure was found to be one of the major factors. When noise frequency is placed on the communication channel, the relevant clock frequency needs to be adjusted to avoid the radio frequency interference (RFI). In this work, we report the simulation-based analysis and modeling to estimate the EMI noise magnitude and its bandwidth of an AP-LPDDR interface prior to silicon characterization. This helps address the potential EMI risks and help select RFI-aware frequency on ICs upfront at the pre-silicon level. Our simulation results were in good agreement with silicon results validating our modeling approach. In order to analyze the EMI effect from AP-LPDDR interface, the IO clock and data signals were modeled with the controllable parameters. By analyzing voltage fluctuations at the memory pad the noise frequency at peak points and their bandwidths were estimated, and by adjusting critical factors such as bits toggle/idle ratio, and burst length, the influence of EMI magnitude and bandwidth have been identified. The approach was validated with measured voltage at the interposer.

Electromagnetic Interference (EMI) is an increasingly important factor in determining whole-system performance of a mobile system. This is driven by size reduction of the mobile platform and the ever-increasing density of electronic components. In this work, we suggest an analysis approach for EMI effects in the interface between an application processor (AP) and dynamic random-access memory (DRAM) by using an I/O driver model including power delivery network (PDN) effects. By applying this approach, the EMI effect by the AP-DRAM interface is able to be accurately estimated when its operating frequency is shifted up/downward depending on the scheme of mobile operations. The EMI effect in the AP-DRAM interface can be characterized by the (1) on-chip metal layout and package layout of the I/O PDN, (2) inserted decoupling capacitance of the I/O PDN, (3) I/O driver properties that define the rising/falling time of signals, and (4) channel properties including crosstalk between adjacent lanes and their frequency response at data transfer. In a time-domain simulation, the extracted I/O driver model was used with extracted AP and memory package models, a channel model, and an interposer. The simulation was carried out by varying input stimulus depending on a bit density ratio, bit length, and a test pattern. As a result, a wide range of spectrum generated by the AP-DRAM interface up to 6 GHz was calculated. The bandwidth of data queue (DQ) signals at the interposer was found to be around 170MHz with multiple harmonics of the fundamental 1.6GHz frequency. In comparison to the measurement, the difference in bandwidth was found to be less than 10MHz and the voltage difference at the harmonics was found to be less than 10dB. Consequently, we proposed an analysis and estimation approach for EMI effects in an AP-DRAM interface which affects the degradation of communication performance in a compact mobile platform and successfully demonstrated its applications for predicting EMI effect in the communication band of interest.

Self-alignment of vertical interconnects using a magnetically aligned anisotropic conductive adhesive (MA-ACA) is a unique method, which is useful in high-density electronic applications.This material is created by magnetic interaction between loading conductive particles in an epoxy medium. To analyze electromagnetic interference between adjacent I/O pads, a lumped component model was suggested, consisting of shunt capacitance, parallel capacitance, series resistance, series inductance, and coupling capacitance. The equivalent circuit model was validated through the measurement of test samples with MA-ACA interconnects. Also, the pad-to-pad isolation of the MA-ACA was compared to that of lead/tin solder connections. As a result, at high frequencies the pad-to-pad isolation of the MA-ACA interconnects was observed to be mainly degraded by a larger coupling capacitance due to the presence of metallic interconnects at a transition region. Therefore, a packaging approach using the characterized RF performance of the MA-ACA interconnects is expected to be designed for high-density electronic circuitry. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:2606–2610, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27153

In this paper, a novel self-assembly packaging approach using a magnetically aligned z -axis anisotropic conductive adhesive (ACA) is introduced, enhancing the quality of interconnects and reducing packaging cost in fine-pitch electronic circuitry. This self-assembly process creates selectively agglomerated vertical columns on I/O pads and is first demonstrated using the magnetization interaction properties between ferromagnetic conductive particles and I/O pads in the presence of an external magnetic field. Experimentally, this packaging process is verified to be particularly beneficial in improving the environmental reliability of the self-aligned material. At 133 × 133-μm pad size, the resistance of the created interconnects only varies by 2.45 Ω over a 160°C temperature range. In addition, the breakdown current of the self-assembly z-axis ACA was measured to be 2.0 A at 1.3 V. Furthermore, this self-assembly process was demonstrated to still work at the extremely small pad size of 12×19-μm. Finally, through analysis of the design parameters of this self-assembly process, properties of the z-axis ACA material and I/O pad structure were suggested to create vertical interconnects for small pads of size in the order of 10 μm.

Characteristics of z-axis interconnects using magnetically aligned anisotropic conductive adhesives (ACAs) are analyzed for their applicability for small pad sizes. In order to evaluate the performance of ACAs, a statistical estimation of the failure rate of interconnects was carried out using top-view images of assembled samples. Through a column mapping process, the failure rate is calculated as a function of pad size. The calculated and measured results indicate that the location of the formed columns is the predominant effect determining interconnect failure. The developed failure estimation approach is effective in demonstrating the effects of scaling to smaller particles in ACAs.

In this paper, the authors present a design technique that enables inter-resonator and external coupling control for high-quality-factor (Q) tunable bandpass filters. The design incorporates low-Q varactors as part of the inter-resonator and external coupling mechanisms without degrading the overall high Q of the original filter. Detailed design methodology and equations are presented to illustrate the concepts. A first-time demonstration of these concepts is presented for a widely tunable high-Q evanescent-mode cavity bandpass filter. The cavities are integrated in a low-loss substrate with commercially available piezoelectric actuators and solid-state varactors for frequency and bandwidth tuning. This technique allows for reduced bandwidth variation over large tuning ranges. As one example, a constant 25-MHz absolute-bandwidth filter in the 0.8-1.43-GHz tuning range with loss that is as low as 1.6 dB is presented as an example. The filter third-order intercept point is between 32.8 and 35.9 dBm over this tuning range. To further show the impact of the technique on high- Q filters, a filter Q that is as high as 750 is demonstrated in the range of 3-5.6 GHz, while using low-Q varactors (Q < 30 at 5 GHz for a 0.4-pF capacitance) to achieve more than 50% reduction in bandwidth variation over the tuning range.

We report live animal studies that verify and quantify successful transocular transmission of data from a miniature low-power implant. To minimize damage, implantation within layers of the eye requires an ultrasmall device on a scale of just a few millimeters on each side and less than 500 mum in thickness. A high-frequency transmitter integrated circuit (IC) was designed, fabricated, and bonded onto a board containing an antenna, matching network components, and interconnects. The transmitter must achieve sufficient efficiency to draw minimal power from the limited onboard storage array while outputting a sufficiently large signal to overcome tissue-induced attenuation. Two different versions of the system were developed, one using a low-temperature co-fired ceramic material for the substrate and the other using silicon. Animal studies performed using live rabbits followed by empirical measurements verified the feasibility of a wireless telemetry scheme for a low-power miniature ocular implant.

Randomly dispersed particles in a material can be forced to align due to the presence of an externally applied field. These self-aligning materials are examples through which order is obtained through structure created internally which alters the bulk properties of the material. One such material is a magnetically aligned anisotropic conductive adhesive which uses the alignment of ferromagnetic particles in order to create current flow in only one direction. This paper discusses microwave application of such a material. We demonstrate that the magnetically aligned Z -axis anisotropic conductive adhesive works at microwave frequencies interconnecting silicon substrates through 90 GHz. The Z-axis material is found to be a suitable replacement for solder bumping even at high frequencies of operation. The effect of material composition and the radio frequency design is discussed in this paper. Finally, the Z -axis anisotropic conductive adhesive is found to be a suitable cost-effective replacement for solder bumps at high frequencies.

In this work, we proposed a novel approach for electrostatic discharge (ESD) noise stress analysis using transfer impedance analysis in a platform for a large-scale integration chip. In the electronic industry an ESD test is widely taken to evaluate the noise immunity of a designed electronic device. In this ESD test, critical hardware damage or functional problems may occur due to temporary electrical disturbances produced by applying an external electrical shock. By manipulating the transfer-impedance difference from a noise-induced point to power/ground points of an IC, the influence of an induced ESD noise that could significantly affect the IC's performance was analyzed. The ESD noise stress affects supply voltage to become unstable in a power delivery network (PDN) and adversely affects analog/digital circuit operations during data processing. The impedance differences in the PDN produces supply voltage instability in a designed chip. Thus, by analyzing the transfer impedance from the PCB to the power nets of a time-controller IC, the variation of supply voltage due to external ESD noise can be estimated. In order to separate noise-to-power and noise-to-ground paths on a PCB, an additional ground layer, which exists only in simulation, was used for estimating temporal voltage fluctuation due to impedance imbalance between the noise-to-power and the noise-to-ground paths. In comparison, the proposed approach was demonstrated to agree with the measurement up to 500 MHz. This estimation result indicated that the simulation approach on ESD noise immunity using transfer impedance is useful to predict the influence of electrical stress to a designed IC on a PCB. The estimation approach on ESD noise impact is expected to be applicable for the PDN design of a PCB/IC to improve its ESD noise immunity prior to its implementation.

Inside an electronic product with high-speed interfaces, a lot of technological effort is required for neutralizing mutual electromagnetic interference (EMI) between adjacent electronic components. Thus, it is necessary to adopt an EMIaware design to maintain high-performance features by avoiding possible EMI causes in a large-scale integration (LSI) chip. In this work, we analyzed IC-level EMI causes for improving on-chip EMI perspectives by characterizing composing channel impedance with a view to the whole system. A test channel for characterizing system-level impedance properties consists of power/ground nets of onchip metal layers, a chip-on film (CoF), and a printed circuit board (PCB). Specifically, we compared two test samples with different features. One (sample 1) has a 0.8nF on-chip decoupling capacitor, only horizontal Vdd-Vss pairing layout for power interconnects, and 0.2T clock shift scheme from data edge position. The other (sample 2) has a 1.5nF on-chip decoupling capacitor, both vertical and horizontal Vdd-Vss pairing layout for confining an EM field, and 0.5T clock shift scheme for frequency spreading effect. Using simulation results and frequency domain analysis, the impedance was found to be 1.3 Ohm to 0.9 Ohm at a specific noise frequency of interest (132MHz) as the decoupling capacitance increases from 0.8 nF to 1.5nF. In comparison, the performance of EMI properties in sample 2 was found to be improved by 6.0dB when compared to sample1. Specifically, this improvement turned out to be affected by 3.2dB due to increasing on-chip decoupling capacitance of 0.7dB due to a shielding effect on the power/ground interconnect layout of an added metal layer and 1.6dB due to changing the scheme of a clock timing transition. In the simulation-based estimation, this 5.5dB improvement was demonstrated to agree with the near-field measurement with a 6.0dB improvement. Consequently, our approach to analyze on-chip EMI effects is helpful to understand complex electromagnetic behaviors in an LSI chip and it is also expected to be applicable in suppressing complex EMI causes for leveraging on-chip EMI performance.

We investigated the electromagnetic compatibility of 155Mb/s optical transceiver module. The margin of 3.4dB for radiated emission and the penalty of 3.0dB for radiation susceptibility were measured for the device and the effect of metallic shielding plate on performance enhancement was also evaluated.

We propose contact rule-based decision criteria to embed on autonomous mobile nodes to mimic mobile users' community contact pattern. To evaluate the closeness to real-world contact pattern, we compare the simulation results to the contact trace of WLAN users from the University of Florida. Our results show that the contact rule-based decision with overlapping community information matches real-world data in terms of contact duration and the periodical contact pattern.

High quality factor W band MEMS-tunable evanescent-mode bandstop resonators are presented for the first time. The precision, tolerances, and small feature capability of silicon microfabrication techniques enable these resonators to be the highest frequency tunable evanescent-mode cavities shown to date. Their MEMS tuning technology requires very low power to operate, and the entire resonator-tuner structure is made of silicon to enable compatibility with integrated circuit manufacturing processes. A measured tuning range of 75.8 GHz to 82.3 GHz with quality factors of 414 to 448 were observed with a tuning voltage of 70 Volts. Such resonators will be important for tunable W band filters as lower frequencies become saturated and W band applications become more common.

We study the encounter patterns of mobile devices to understand the potential of mobile nodes as messengers in delay tolerant networks. Specifically, we examine the extensive network and encounter traces that reflect mobility of communication devices, using spectral analysis to unearth hidden repetitive patterns of them. We discover strong presence of periodic encounter patterns between mobile users, particularly weekly pattern. Our results also show different location visiting ratio by more than 10 percent between regularly encountering pairs and others at 77 percent of the locations.

In this letter, the design and RF packaging of substrate integrated widely tunable filter is presented. The filter consists of two heavily loaded evanescent-mode cavities embedded into the substrate. The filter is actuated using two piezoelectric discs, which move thin, flexible membranes that form the top of the cavities. To demonstrate the wide tuning a filter is fabricated and measured to cover a very wide frequency range from 0.98 to 3.48 GHz (tuning ratio-3.55:1). The measured insertion loss is less than 3.57 dB for a 1.1% fractional bandwidth filter.

We present the packaging of a 1.25-Gb/s bidirectional transceiver using a filter-integrated planar lightwave circuit (PLC) platform for passive optical networks. A simple packaging for a hybrid transceiver is successfully demonstrated by using a PLC platform with the trench for photodiode (PD) insertion and the adiabatic wavelength division multiplexing (WDM) filter. This transceiver exhibited full-duplex operation of 1.25 Gb/s with a minimum optical sensitivity of −26.5 dBm under an output power of 0 dBm. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 489–491, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21387

A 1.25-Gb/s bidirectional transceiver is designed and fabricated on a filter-integrated PLC platform for access networks. The fabricated transceiver has optical output of 2.2 dBm at 30 mA and minimum sensitivity of −22.7 dBm at 10−12 at a 1.25-Gb/s NRZ signal and crosstalk penalty of 0.8 dB. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 47: 34–36, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21073