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272 results on '"Swartzlander, Earl E."'

4. Security Issues in QCA Circuit Design - Power Analysis Attacks

Author

Liu, Weiqiang, Srivastava, Saket, O’Neill, Máire, Swartzlander, Earl E., Jr., Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Kobsa, Alfred, Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Anderson, Neal G., editor, and Bhanja, Sanjukta, editor

Published
2014
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19. A reduced complexity wallace multiplier reduction

Author

Waters, Ron S. and Swartzlander, Earl E.

Subjects
Adders (Electronics) -- Usage, Computational complexity -- Evaluation, Multipliers (Electronics) -- Speed, Multipliers (Electronics) -- Design and construction
Published
2010

20. Adder and multiplier design in quantum-dot cellular automata

Author

Cho, Heumpil and Swartzlander, Earl E.

Subjects
Standard IC, Semiconductor device, Integrated circuits -- Design and construction, Semiconductor chips -- Design and construction, Quantum electrodynamics -- Analysis
Published
2009

21. Digit-pipelined direct digital frequency synthesis based on differential CORDIC

Author

Kang, Chang Yong and Swartzlander, Earl E., Jr.

Subjects
Algorithms -- Analysis, Frequencies of oscillating systems -- Research, Algorithm, Business, Computers and office automation industries, Electronics, Electronics and electrical industries
Abstract

A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed. Index Terms--Digit-level pipelining, direct digital frequency synthesis (DDFS), differential CORDIC (DCORDIC), on-line arithmetic, systolic array.

Published
2006

23. A scaled DCT architecture with the CORDIC algorithm

Author

Yu, Sungwook and Swartzlander, Earl E., Jr.

Subjects
Signal processing -- Research, Very-large-scale integration -- Research, Algorithms -- Research, Electronics industry -- Research, Digital signal processor, Business, Computers, Electronics, Electronics and electrical industries
Abstract

An efficient procedure is proposed for computing the N-point (N = 2[superscript n]) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. A DCT architecture is proposed that does not requre scale factor compensation.

Published
2002

24. A pipelined architecture for the multidimensional DFT

Author

Yu, Sungwook and Swartzlander, Earl E., Jr

Subjects
Signal processing -- Research, Fourier transformations -- Research, Processor architecture -- Research, Business, Computers, Electronics, Electronics and electrical industries
Abstract

An efficient pipelined architecture is proposed for the N [superscript m]-point m-dimensional discrete Fourier transform (DFT).

Published
2001

29. Hybrid CORDIC algorithms

Author

Wang, Shaoyun, Piuri, Vincenzo, and Swartzlander, Earl E. Jr

Subjects
Algorithms -- Usage, Iterative methods (Mathematics) -- Usage
Published
1997

32. A spanning tree carry lookahead adder

Author

Lynch, Thomas and Swartzlander, Earl E., Jr.

Subjects
Adders, Computer Arithmetic, Arithmetic logic unit, Scientific Research, Technology, Adders (Electronics) -- Research, Arithmetic logic unit -- Research
Published
1992

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