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Future information technology demands ever-faster, low-loss quantum control. Intense light fields have facilitated milestones along this way, including the induction of novel states of matter.sup.1-3, ballistic acceleration of electrons.sup.4-7 and coherent flipping of the valley pseudospin.sup.8. These dynamics leave unique 'fingerprints', such as characteristic bandgaps or high-order harmonic radiation. The fastest and least dissipative way of switching the technologically most important quantum attribute--the spin--between two states separated by a potential barrier is to trigger an all-coherent precession. Experimental and theoretical studies with picosecond electric and magnetic fields have suggested this possibility.sup.9-11, yet observing the actual spin dynamics has remained out of reach. Here we show that terahertz electromagnetic pulses allow coherent steering of spins over a potential barrier, and we report the corresponding temporal and spectral fingerprints. This goal is achieved by coupling spins in antiferromagnetic TmFeO.sub.3 (thulium orthoferrite) with the locally enhanced terahertz electric field of custom-tailored antennas. Within their duration of one picosecond, the intense terahertz pulses abruptly change the magnetic anisotropy and trigger a large-amplitude ballistic spin motion. A characteristic phase flip, an asymmetric splitting of the collective spin resonance and a long-lived offset of the Faraday signal are hallmarks of coherent spin switching into adjacent potential minima, in agreement with numerical simulations. The switchable states can be selected by an external magnetic bias. The low dissipation and the antenna's subwavelength spatial definition could facilitate scalable spin devices operating at terahertz rates. Antenna-enhanced terahertz pulses ballistically switch spins in antiferromagnetic TmFeO.sub.3 with minimal energy dissipation between metastable minima of the anisotropy potential, as characterized by unique temporal and spectral fingerprints., Author(s): S. Schlauderer [sup.1] , C. Lange [sup.1] , S. Baierl [sup.1] , T. Ebnet [sup.1] , C. P. Schmid [sup.1] , D. C. Valovcin [sup.2] , A. K. Zvezdin [...]

A fully integrated soft-start circuit for voltage regulators is presented in this brief. A soft-start strategy based on a linearly ramped-up reference is adopted to prevent massive inrush currents through the power device during the start-up phase of the regulator. The strategy is realized by a compact on-chip circuit, which requires no external components and has minimal transistor overhead, thereby minimizing the implementation area and cost of the overall regulator. The proposed soft-start circuit has been implemented in a 0.35-[micro]m high-voltage complementary metal-oxide-semiconductor technology as part of a linear regulator controller for automotive applications. The proposed soft-start circuit occupies 0.026 [mm.sup.2] on silicon, which corresponds to about one fifteenth of the total area of the linear regulator controller. Index Terms--Linear regulator, low-dropout regulator (LDO), power management integrated circuits, soft start, switching regulator, voltage regulators.

We investigate the [L.sub.2] gain of periodic linear switched systems under fast switching. For systems that possess a suitable notion of a time-average system, we characterize the relationship between the [L.sub.2] gain of the switched system and the [L.sub.2] gain of its induced time-average system when the switching rate is sufficiently fast. We show that the switched system [L.sub.2] gain is in general different from the average system [L.sub.2] gain if the input or output coefficient matrix switches. If only the state coefficient matrix switches, the input-output energy gain for a fixed [L.sub.2] input signal is bounded by the [L.sub.2] gain of the average system as the switching rate grows large. Additionally, for a fixed [L.sub.2] input, the maximum pointwise in time difference between the switched and average system outputs approaches zero as the switching rate grows. Index Terms--Fast switching, [L.sub.2] gain analysis, switched systems.

A novel, low-loss, constant-frequency, zero-voltage-switching (ZVS) modulation strategy for bidirectional, cascaded, buck--boost dc--dc converters, used in hybrid electrical vehicles or fuel cell vehicles (FCVs), is presented and its benefits over state-of-the-art converters and soft-switching solutions are discussed in a comparative evaluation. To obtain ZVS with the proposed modulation strategy, the buck + boost inductance is selected and the switches are gated in a way that the inductor current has a negative offset current at the beginning and the end of each pulse period. This allows the MOSFET switches to turn on when the antiparallel body diode is conducting. As the novel modulation strategy is a software-only solution, there are no additional expenses for the active or passive components compared to conventional modulation implementations. Furthermore, an analytical and simulation investigation predicts an excellent efficiency over the complete operating range and a higher power density for a nonisolated multiphase converter equipped with the low-loss modulation. Experimental measurements performed with 12 kW, 17.4 kW/L prototypes in stand-alone and multiphase configuration verify the low-loss operation over a wide output power range and a maximum efficiency of 98.3% is achieved. Index Terms--DC-DC power conversion, fuel cells, power conversion.

The dynamic behaviors of a nonlinear second-order digital filter with two's complement arithmetic under periodic inputs are explored. The conditions for avoiding overflow are derived. Various dynamic periodic responses are analyzed, accompanied by numerous simulation examples. Index Terms--Chaos, dynamic symbolic sequence, nonlinear digital filter, overflow, switching system.

Among converter control techniques, the direct current tracking methods give fast and accurate response with good dynamic performance. Unfortunately, in multiswitching systems, these techniques have certain drawbacks. In particular, when the number of controlled switching elements is greater than the number of independent currents, undesirable interactions arise between the control algorithms. This paper proposes a general and systematic approach to decouple the controlled currents. This allows us to adopt simpler current tracking strategies (not discussed in this paper) for each controlled switching element even in complex multiswitching converters. Independence between lower level switching algorithms is achieved by means of a set of decoupling variables. Simulation and experimental results from a case study are reported. Index Terms--Current control of multiconverters, switching strategies.

The switching behavior of power converters with 'ideal' electronic devices (EDs) makes it difficult to define a switched model that describes the dynamics of the converter in all possible operating conditions, i.e., a 'complete' model. Indeed, simplifying assumptions on the sequences of modes are usually adopted, also in order to obtain averaged models and discrete--time maps. In this paper, we show how the complementarity framework can be used to represent complete switched models of a wide class of power converters, with EDs having characteristics represented by piecewise-affine (even complicated) relations. The model equations can be written in an easy and compact way without the enumeration of all converter modes, eventually formalizing the procedure to an algorithm. The complementarity model can be used to perform transient simulations and time-domain analysis. Mathematical tools coming from nonlinear programming allow to simulate numerically the transient behavior of even complex power converters. Also rigorous time-domain analysis is possible without excluding pathological situations like, for instance, inconsistent initial conditions and simultaneous switchings. Basic converter topologies are used as examples to show the construction procedure for the complementarity models and their usefulness for simulating the dynamic evolution also for nontrivial operating conditions. Index Terms--Modeling, piecewise linear approximation, power conversion, simulation, switched systems, switching circuits.

A new high-efficiency and high-power bilateral buck and boost chopper circuit for the electric-vehicle drive application is presented. The operation principle of snubber-assisted zero-voltage and zero-current transition (SAZZ) topology was applied, and a new SAZZ bilateral buck-boost chopper circuit (SAZZ-1) was created by combining two basic SAZZ circuit types. A 50-kHz 25-kW SAZZ-1 was fabricated and tested. An efficiency of 96.6% at 25 kW with boost mode (input: 250 V/output: 390 V) in forward direction and an efficiency of 97.4% at 25 kW with buck mode (input: 420 V/output: 300 V) in forward direction were obtained. The high potentiality of the SAZZ-1 chopper is demonstrated as we expected. Index Terms--DC-DC power conversion, insulated-gate bipolar transistor (IGBT).

This paper introduces an approach to near timeoptimal control for synchronous buck dc--dc converters. The proposed proximate time-optimal digital (PTOD) controller is a combination of a constant-frequency pulsewidth modulation (PWM) controller employing a linear PID compensator close to a reference point, and a linear or nonlinear switching surface controller (SSC) away from the reference, together with smooth transitions between the two. A hybrid capacitor current estimator enables switching surface evaluation and eliminates the need for current sensing. The SSC, which is implemented as a small Verilog HDL module, can be easily added to an existing digital PWM controller to construct the PTOD controller. In steady state, the controller operates exactly the same as a standard constant-frequency PWM controller with a linear PID compensator. Simulation and experimental results are shown for a 6.5 V-to-l.3 V, 10 A synchronous buck converter. Index Terms--Boundary control, dc-dc converters, digital control, switching surface control, time-optimal control.

This paper presents a nonlinear average current control method that regulates the true average of the inductor current by using the switch current as the feedback signal. The method is simple, requires no compensator design, and is very insensitive to switching noise. It combines the advantages of both peak current and linear average current control while overcoming their limitations. It can be used in both buck- and boost-derived topologies for a variety of applications requiring precise control of the input or output current, including battery charging using buck-derived topologies and power conditioning for solar and fuel cells using boost-derived topologies. Numerical simulation and experimental measurement results are presented along with theoretical development and analysis to demonstrate the operation principle and performance of the control method. Performance and general control characteristics of the method are also compared with existing linear average current control by using an averaged model. Switch current sensing methods for use with the control are also reviewed. Index Terms--Power factor correction (PFC).

In recent years, network applications and hardware technology have been developed in impressive speed. That is, a large-scale network switching system is needed to satisfy all demand among network service providers and population, such as data, voice, image, video on demand, videoconferencing, telecommunications, remote control and teaching, etc. A general large-scale network switching system cannot fulfill various application needs, such as the correctness of data transmission and the capacity of extension for input/output port of switching system. In this paper, we propose a nested ring-based architecture to build a very large-scale network switching system. In order to satisfy the various network application needs, a nested ring-based architecture is designed as a switching element. It can make input data exchange fast to the destined output port, and input/output port of switching system can easily be extended up to 100 ports or 1000 ports to construct a very large-scale network switching system. The simulation results show that a better performance can be achieved in data transmission, delay, throughput and extensibility for the proposed system. Keywords: A nested ring-based architecture; A very large-scale network switching system

In this paper, the advantages of a new resonant driver are verified thoroughly by the analytical analysis, simulation and experimental results. A new accurate analytical loss model of the power metal oxide semiconductor field effect transistor driven by a current-source resonant gate driver is developed. Closed-formed analytical equations are derived to investigate the switching characteristics due to the parasitic inductance. The modeling and simulation results prove that compared to a voltage driver, a current-source resonant driver significantly reduces the propagation impact of the common source inductance during the switching transition at high (> 1 MHz) switching frequency, which leads to a significant reduction of the switching transition time and the switching loss. Based on the proposed loss model, a general method to optimize the new resonant driver is proposed and employed in the development of a 12 V synchronous buck voltage regulator (VR) prototype at 1 MHz switching frequency. The level-shift circuit and digital implementation of complex programmable logic device (CPLD) are also presented. The analytical modeling matches the simulation results and experimental results well. Through the optimal design, a significant efficiency improvement is achieved. At 1.5 V output, the resonant driver improves the VR efficiency from 82.7% using a conventional driver to 86.6% at 20 A, and from 76.9% using a conventional driver to 83.6% at 30 A. More importantly, compared with other state of the art VR approaches, the new resonant driver is promising from the standpoints of both performance and cost-effectiveness. Index Terms--Resonant gate driver, switching loss model, voltage regulator (VR).

AIGaN/GaN heterojunction field effect transistors (HFETs) are expected to be a good candidate for power switching application at high temperatures. We designed and fabricated a discrete HFET package and a half bridge module using the AIGaN/GaN HFETs and SiC Schottky barrier diodes (SBDs) for high temperature applications. The half bridge module exhibited good reliability after 250 [degrees]C and 400 h high temperature storage. Switching characteristics of the AIGaN/GaN HFET were investigated. Qg x Run, which shows a figure of merit of switching operation, was more than 10 times better than commercial Si MOSFETs. The switching characteristics of the HFET showed no significant degradation up to 225[degrees]C. Index Terms--GaN, heterojunction field effect transistors (HFETs), high temperature, switching.

This paper proposes a novel three-phase ac--dc buckboost converter. The proposed converter uses four active switches, which are driven by only one control signal. This converter is operated in discontinuous conduction mode (DCM) by using the pulsewidth modulation (PWM) technique, and the control scheme very easily and simply achieves purely sinusoidal input current, high power factor, low total harmonic distortion of the input current (TH[D.sub.i]) and step-up/down output voltage. Also, the proposed converter provides a constant average current to the output capacitor and load in each switching period. Thus, the ripple component of sixth times line frequency will not appear in the output voltage. Therefore, a smaller output capacitor can be used in the proposed converter. Moreover, the steady-state analysis of voltage gain and boundary operating condition are presented. Also, the selections of inductor, output capacitor and input filter are depicted. Finally, a prototype circuit with simple control logic is implemented to illustrate the theoretical analysis. Index Terms--Buck-boost converter, discontinuous conduction mode (DCM), pulsewidth modulation (PWM), TH[D.sub.i].

This paper presents the design of a novel wide output current range dual-mode dc to dc step-down (Buck) switching regulator/converter. The converter can adaptively switch between pulsewidth modulation (PWM) and pulse-frequency modulation (PFM) both with very high conversion efficiency. Under light load condition the converter enters PFM mode. The function of closing internal idle circuits is implemented to save unnecessary switching losses. The converter can be switched to PWM mode when the load current is greater than 100 mA. Soft start operation is designed to eliminate the excess large current at the start up of the regulator. The chip has been fabricated with a TSMC 2P4M 0.35 [micro]m polycide CMOS process. The range of the operation voltage is from 2.7 to 5 V, which is suitable for single-cell lithium-ion battery supply applications. The maximum conversion efficiency is 95 % at 50 mA load current. Above 85 % conversion efficiency can be reached for load current from 3 to 460 mA. Index Terms--Buck converter, dual-mode converter, integrated power management, pulse-frequency modulation (PFM), pulsewidth modulation (PWM).

In this paper, a new current source gate drive circuit is proposed for power MOSFETs. The proposed circuit achieves quick turn on and turn off transition times to reduce switching loss and conduction loss in power MOSFETs. In addition, it can recover a portion of the C[V.sup.2] gate energy normally dissipated in a conventional driver. The circuit consists of four controlled switches and a small inductor (typically 100 nH or less). The current through the inductor is discontinuous in order to minimize circulating current conduction loss. This also allows the driver to operate effectively over a wide range of duty cycles with constant peak current--a significant advantage for many applications since turn on and turn off times do not vary with the operating point. Experimental results are presented for the proposed driver operating in a boost converter at 1 MHz, 5 V input, 10 V/5 A output. At 5 V gate drive, a 2.9% efficiency improvement is achieved representing a loss savings of 24.8% in comparison to a conventional driver. Index Terms--Metal oxide semiconductor field effect transistor (MOSFET), root mean square (RMS), zero voltage switching (ZVS).

This paper introduces a voltage mode digital controller for low-power high-frequency dc-dc switch-mode power supplies (SMPS) that has fast transient response, approaching physical limitations of a given power stage. In steady state, the controller operates as a conventional pulsewidth modulation regulator and during transients it utilizes a novel fast voltage recovery mechanism, based on real-time processing of the output voltage in digital domain. This continuous-time digital signal processing mechanism is implemented with a very simple processor consisting of a set of asynchronous comparators, delay cells, and combinatorial logic. To eliminate the need for current measurement and calculate the optimal switching sequence of the power stage transistors, the processor performs a capacitor charge balance algorithm, which is based on the detection of the output voltage peak/valley point. The effectiveness of the controller is demonstrated on an experimental 5 W, 5 V to 1.8 V, 400 kHz buck converter. The converter recovers from load transients through a single on-off action of the power switch, virtually reaching the shortest possible time, limited by the values of the power stage filter components only. Index Terms--Low-power dc-dc converters, digital control, continuous-time digital signal processing, capacitor charge-balance.

A major consideration in designing controllers for boost converters is the existence of a right-half-plane zero in the control-to-output transfer function. This property makes the controller impossible to be designed in classical frequency-domain approach to achieve fast dynamic response over wide bandwidth of supply and load variations. In this paper, a time-domain boundary control concept for large-signal control of boost converters is proposed. By transforming the conventionally used state plane into the newly proposed state-energy plane to dictate the switching instants, a well-defined switching surface is derived. The converter can ideally revert to the steady state in two switching actions when it is subject to external disturbances. Of particular importance, experiments show that the same controller is applicable for controlling converters operating in continuous conduction mode, critical conduction mode, or discontinuous conduction mode. Sensitivities of the switching surface to parametric variations will be studied. Theoretical predictions will be verified with the experimental results of a 55 W, 48 V/110 V prototype. Index Terms--Boost converters, boundary control, control theories, dc/dc conversion.

The high switching activity of wide fan-in dynamic domino gates introduces significant power overhead that poses a limitation on using these compact high-speed circuits. This paper presents a new limited-switching clock-delayed dynamic circuit technique, called SP-Domino, which achieves static-like switching behavior, while maintaining the low-area and high-performance characteristics of wide fan-in dynamic gates. SP-Domino is a single-phase footless domino that can be freely mixed with static gates and can provide inverting and non-inverting functions. Simulations on 8 and 16 inputs OR gates show that SP-Domino reduces dynamic power by up to 63% compared to same-UNG and same-delay standard footless domino, and up to 56.9% compared to low-contention high-speed standard footless domino. Index Terms--Domino logic, dynamic circuits, low power, switching activity.

RF pulsewidth modulation (PWM) has been proposed as an efficiency improving technique for power amplifiers (PAs) handling varying envelope signals. The core idea is to modulate the varying envelope into a square-wave signal such that the width of each pulse is varied according to the envelope, and any phase information is contained in the timing of the pulses. The square wave signal can give a theoretical efficiency of 100% for the subsequent PA. Such a system differs significantly from a conventional up-conversion and PA and, therefore, a significant design challenge results. The first important step is to generate the PWM signal. This paper demonstrates a functional modulator for Universal Mobile Telecommunications System operating at 2 GHz. The modulator is designed in a GaAs HBT process and uses low-frequency feedback combined with predistortion to obtain a high spectral purity. Measurements show a Universal Mobile Telecommunications System PWM signal with more than 10-dB margin to the modulation mask and an error vector magnitude of less than 1.5 % rms (requirement: 17.5%). Index Terms--Class D, class E, modulator, power amplifier (PA), RF pulsewidth modulation (RF PWM), switch mode.

This brief presents a new switching converter operating in pseudo-continuous-conduction mode (PCCM) with freewheel switching control. Compared with conventional discontinuous-conduction mode (DCM) converters, this converter demonstrates much improved current handling capability with reduced current and voltage ripples. The control-to-output transfer function exhibits a single-pole behavior, making the load transient response much faster than its CCM counterparts. Simulation and experimental results show that, with a 6-V, 6-W load and a 10-V unregulated supply, the PCCM converter has a current ripple of only 1.1 A and a ripple voltage of only 58 mV, while a DCM converter has a current ripple of 2.2 A and a ripple voltage of 220 mV. In addition, the PCCM converter takes only 25 [micro]s to respond to a 500-mA load current change while a CCM one requires 1.4 ms. Index Terms--Current ripple, freewheel switching, pseudo-continuous-conduction mode (PCCM), switching converter, transient response, voltage ripple.

A novel auxiliary switch dc-dc converter with coupled inductor is presented in this paper. The proposed circuit achieves loss-less switching for both the main and auxiliary switches without increasing the main device current/voltage rating. A tapping in the pole inductor is added for the purpose of commutation. The proposed circuit is capable of operation at elevated switching frequencies of several hundreds of kHz, in a range of line and load variations. The proposed circuit is applicable to all isolated and non-isolated dc-dc converters. The performance and the design equations of the ZVS are identical for all types of dc-dc converters when the throw voltage and the pole current are properly defined. In the sections that follow, operating principle and theoretical analysis of the proposed circuit is outlined through the example of buck converter. Simulation and experimental results of 33 W,400 kHz boost converter are presented. Index Terms--Auxiliary switch converters, coupled inductor, resonant converters, zero current switching (ZCS), zero voltage switching (ZVS).

To investigate the high-frequency behaviors for the switching converters, the modeling and analysis should include the influences from the sideband components, which are generated by the converter's nonlinearities. With a buck converter, two non-linearities are identified in this paper: the pulse-width modulator and the switches. Based on the harmonic-balance approach, the multifrequency model is proposed to address these nonlinearities and to predict the high-frequency performances. With the derived model, different modulation schemes are compared based on their influence on the sideband effect and the control bandwidth limitations. The possible benefit from the double-edge modulation and its limitations are clarified. In addition, the audio-susceptibility is studied considering the nonlinearity of the switches. With the combination of the two nonlinearities, a generic high-frequency model is achieved. Simulation and experimental results are presented to verify the achievements of the proposed models. Index Terms--Buck converter, high frequency, modeling, non-linear.

A monolithic current-mode pulse width modulation (PWM) step-down dc-dc converter with 96.7% peak efficiency and advanced control and protection circuits is presented in this paper. The high efficiency is achieved by 'dynamic partial shutdown strategy' which enhances circuit speed with less power consumption. Automatic PWM and 'pulse frequency modulation' switching boosts conversion efficiency during light load operation. The modified current sensing circuit and slope compensation circuit simplify the current-mode control circuit and enhance the response speed. A simple high-speed over-current protection circuit is proposed with the modified current sensing circuit. The new on-chip soft-start circuit prevents the power on inrush current without additional off-chip components. The dc-dc converter has been fabricated with a 0.6 [micro]m CMOS process and measured 1.35 m[m.sup.2] with the controller measured 0.27 m[m.sup.2]. Experimental results show that the novel on-chip soft-start circuit with longer than 1.5 ms soft-start time suppresses the power-on inrush current. This converter can operate at 1.1 MHz with supply voltage from 2.2 to 6.0 V. Measured power efficiency is 88.5-96.7% for 0.9 to 800 mA output current and over 85.5% for 1000 mA output current. Index Terms--Compensation ramp, current sensing, current-mode control, over-current protection, power management, pulse frequency modulation (PFM), pulse width modulation (PWM), soft-start, switching dc-dc converter.

In modern high-power medium voltage drives, multilevel converters are increasingly used. Employing slight topological modifications, soft-switching technology can be applied to multilevel converters to reduce the switching losses. As a result, the switching frequency can be increased, thereby reducing the output filter size. However, common converter controls have to be modified. In this paper, a flexible control platform is presented that allows rapid prototyping of soft-switching topologies. An analysis of different auxiliary resonant commutated pole (ARCP) topologies shows that all switching commands can be synthesized with synchronized signals of two-level ARCP converters. Therefore, a flexible state-machine for two-level converters was developed first, which can also be used to build controls for multilevel topologies. It supports drivers with built-in intelligence as well as the control of additional switches that are required in some ARCP neutral-point-clamped (NPC) topologies. The switching commands for the state machines can be generated by standard multilevel modulation methods. Illegal switching states are filtered and multiple simultaneous commutations per phase are prevented for ARCP NPC converters. To verify the functionality, the control scheme was realized in a field programmable gate array and a completely modular test converter was developed. This test converter can be used to quickly implement all common multilevel topologies and test different modulation strategies. Experimental results are presented in this paper. Index Terms--Auxiliary resonant commutated pole (ARCP) topologies, diode-clamped-multilevel (DCML) inverter, field programmable gate array (FPGA), neutral-point-clamped (NPC) topologies, pulsewidth modulation (PWM) inverter.

A high-order switching surface for boundary control of inverters is presented in this paper. The concept is based on using the natural response of the power stage to formulate a logarithmic function to approximate the ideal switching surface. With the proposed control method, the inverter exhibits better dynamic responses than the ones with the first-order or recently proposed second-order switching surfaces. It will also be shown that the first-order and second-order switching surfaces are the low-order approximations of high-order switching surface. As the high-order switching surface is close to the ideal switching surface, its high trajectory velocity along the switching surface makes the inverter state trajectory move toward the steady-state operating point in two switching actions under large-signal disturbances. The effects of the parametric variations on the output voltage and the large-signal characteristics of the inverter will be discussed. The proposed control method has been successfully applied to a 300-W, ll0-V, 60-Hz, single-phase full-bridge inverter. The steady-state and large-signal dynamic behaviors of the inverter supplying to resistive, nonlinear inductive, and full-wave rectifier loads will be given. Index Terms--Boundary control, dc-ac converter, inverters, nonlinear control.

The bottleneck of digital control for power factor correction (PFC) implementations is mainly due to three aspects: high calculation requirements, high cost, and limited switching frequency compared with analog implementations. A new duty cycle control strategy for boost PFC implementations is proposed in this paper. The duty cycle is determined based on the input voltage, reference output voltage, inductor current, and reference current. The duty cycle determination algorithm includes two terms, the current term and the voltage term, which can be calculated in parallel and requires only one multiplication and three additions (subtractions) operations in digital implementation. A 400-kHz switching frequency boost PFC based on field programmable gate array implementation and its test results show that the proposed new duty cycle control strategy has great potential in the next generation of high switching frequency PFC implementations, due to its lower calculation requirement, lower cost, and better performance than the conventional PFC control methods. Index Terms--Field programmable gate array (FPGA), power factor correction (PFC), switched mode power supplies (SMPS).

This paper focuses on the development of the natural balancing theory for the p-cell case. It describes the relationship between the models for different numbers of cells in a generic model for a p-cell multicell converter. The model discussed is based on the same principles that were used to develop the two-cell model in [16], except that the mathematics is much more involved. The same conclusions that were found to be true for the two-cell case was also found to be true for the general case of p cells. These conclusions include that the natural balancing mechanism of multicell converters depends on the overlap of the groups of harmonics of the switching function as well as on the load impedance. It will also be shown that the self-balancing mechanism ensures safe operation under most operating conditions where a high enough switching frequency is chosen and the load is not purely reactive. Two new aspects of the balancing theory were identified in the p-cell case: 1) for fixed duty-cycle modulation there exists certain values of the duty-cycle that causes the natural balancing mechanism to fail and 2) for p-cell converters the balance booster concept can be extended to a number of balance boosters tuned to multiples of the switching frequency. A 'Design Tool' based on the balancing theory was developed to aid practicing engineers in designing multicell converters. Index Terms--p-cell, two-cell case.

The three-phase Delta-Rectifier is formed by a delta-connection of single-phase pulsewidth modulation (PWM) rectifier modules and has the advantage that it can provide full rated output power in the case of a mains phase loss. In this paper the Delta-Rectifier, implemented with a standard (two-level and/or three-level) boost converter, is analyzed based on an equivalent star connection. Analysis of the Delta-Rectifier shows a redundancy in the switching states concerning the input voltage formation. Furthermore, the Delta-Rectifier has reduced current ripple in the mains phase currents if the modulation is implemented with synchronized PWM. A disadvantage of two-level Delta-Rectifier is the higher voltage stress on the switching devices; however this is mitigated when the boost converter is implemented with a three-level topology as realized for a 10.5-kW laboratory prototype. The Delta-Rectifier concept is proposed based on theoretical considerations and is verified experimentally. The influence of non-idealities on the current ripple formation in the practical realization is analyzed and a high quality mains phase current is demonstrated. Index Terms--Pulsewidth modulation (PWM), total harmonic distortion (THD).

This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fault detection and identification methods for this type of system are provided, by using a state-space approach to asynchronously switching systems. Index Terms--Digital circuits, discrete systems, networks, synchronization.