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This paper proposes a design-oriented DC model for MOS transistors in advanced nanometric technologies, based on only six parameters. The proposed model is based on the inversion charge and includes the main short-channel effects for accurately describing the behavior of the transistor DC drain current in all regions (linear to saturation) and regimes of operation (weak to strong inversion). The proposed model is critically compared to existing inversion charge-based models, highlighting the main limitations of previous models presented in the literature and the advantages and disadvantages of our proposal. Then, regarding the model implementation, previously presented inversion charge-based models require a numerical solver to link the transistor’s DC current to its DC node voltages. In this work, we propose an innovative approach to model implementation via the analytical approximation of the Lambert function’s principal branch. Thanks to this approximation, the proposed design-oriented model offers for the first time an analytical single-piece expression of the drain current as an explicit function of the transistor node voltages. The validity of both the proposed transistor DC model and its analytical single-piece implementation is confirmed through simulation and measurement results, using the industrial production-level model UTSOI2 as a reference. The evaluations were conducted on MOS transistors with lengths of 30nm, 60nm, and 150nm in STMicroelectronics 28nm FD-SOI CMOS technology, to validate our results in minimum length, intermediate length, and long transistors in the selected technology. The proposed model achieves an average error of less than 6% in drain current evaluation compared to industry-standard models such as UTSOI2, while significantly reducing computational complexity.

This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than $20~\%$ in the DC currents and $30~\%$ in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4 GHz low-noise-amplifier in a 28 nm FD-SOI CMOS technology. Obtained results in terms of $S_{11}$ , $S_{21}$ , NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.

Abstract In this paper, a 2‐bit digital reflection‐type phase shifter (RTPS) working at 120 GHz is presented. It uses a compact coupled‐lines coupler with low insertion loss and high isolation over a wide bandwidth. The loads are made by a microstrip‐line loaded by three PN jonction separated by an intermediate region I (PIN) diodes whose states are tuned ON/OFF to obtain 90°, 180° and 270° phase shift relative to the reference (0°). Measurement results show root mean square (RMS) phase and amplitude error equal to 10.3° and 1.2 dB, respectively. The maximum insertion loss is equal to 8.6 dB, leading to a figure of merit of 31°/dB. As shown by simulation, by flipping PIN diodes and using negative voltage for biasing, the maximum insertion loss could be reduced to 3.6 dB (figure of merit of 75°/dB) along with a great improvement in RMS phase and amplitude errors, thus showing the potential of the proposed architecture.

This paper presents a 7-parameter analytical model of the MOS transistor based on the inversion charge targeted at the development of simplified analytical circuit design methodologies that take into account the physics of the MOS transistor. The proposed design-oriented model allows for the first time to describe both the main short-channel effects of advanced nanometric technologies and the dependence of the transistor drain current on the drain voltage, while the model remains valid for all bias regimes (from weak to strong inversion) and for all operating regions (linear and saturated). A simple procedure based on the device physics is proposed to estimate the transistor model parameters for a given technology. Furthermore, analytical expressions of the current derivatives are developed targeting different design scenarios. The accuracy of the proposed model is validated by direct comparison to silicon measurements of N-MOS transistors in 28 nm FD-SOI technology for channel width of $1~\mu \text{m}$ and channel lengths of 30 nm, 60 nm and 150 nm, and also to simulations performed with an industry-standard compact model.

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This paper presents the study, design and simulation of a multi-flow radio frequency transceiver based on a direct sequence spread-spectrum with a 2.4 GHz carrier. First, the functional model of differential QPSK modulation for digital transmission, and the different parts making up spread spectrum function (spreader, despreader, tracking and synchronising devices) have been studied, implemented, simulated and validated in noisy multi-users and multi-path environment by using a unified language. The results obtained by taking into account the home automation running constraints have allowed to determine some critical parameter values and so to integrate the digital functions in an ASIC circuit.