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378 results on '"TITARENKO, LARYSA"'

1. Reducing the Number of Luts for Mealy FSMS with State Transformation

Author: Barkalov Alexander, Titarenko Larysa, and Mielcarek Kamil
Subjects: mealy fsm, fpga, lut, synthesis, extended state codes, combined state codes, Mathematics, QA1-939, Electronic computers. Computer science, QA75.5-76.95
Abstract: In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of the most important characteristics used in logic synthesis. In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes). The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states.
Published: 2024
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2. VLSI-based Logic Synthesis

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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3. Control Algorithms and Finite State Machines

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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4. FPGA-Based Synthesis of CFSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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5. Optimization of ASIC-based CFSMs Finite State-Machine (FSM) combined (CFSM)

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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6. CPLD-Based Synthesis with Transformation of State Codes

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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7. Homogenous CPLD-Based Synthesis Synthesis of CFSMs Finite State-Machine (FSM) combined (CFSM)

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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8. Heterogeneous CPLD-based Synthesis of CFSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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9. ASIC-based Synthesis of CFSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, Kawecka, Elżbieta, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Li, Yong, Series Editor, Liang, Qilian, Series Editor, Martín, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Oneto, Luca, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zamboni, Walter, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Mazurkiewicz, Małgorzata, and Kawecka, Elżbieta
Published: 2022
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10. Improving the LUT Count for Mealy FSMS with Transformation of Output Collections

Author: Barkalov Alexander, Titarenko Larysa, and Mazurkiewicz Małgorzata
Subjects: mealy fsm, fpga, lut, synthesis, state codes, Mathematics, QA1-939, Electronic computers. Computer science, QA75.5-76.95
Abstract: A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from 9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more pronounced with increasing values of FSM inputs and state variables.
Published: 2022
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11. Combining Twofold State Assignment with Transformation of Object Codes

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Chmielewski, Sławomir, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, and Chmielewski, Sławomir
Published: 2020
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12. Mixed Encoding of Microoperations

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Chmielewski, Sławomir, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, and Chmielewski, Sławomir
Published: 2020
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13. Synthesis of Mealy FSMs with Counters

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Chmielewski, Sławomir, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, and Chmielewski, Sławomir
Published: 2020
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14. Twofold State Assignment for Moore FSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Chmielewski, Sławomir, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, and Chmielewski, Sławomir
Published: 2020
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15. Combining Twofold State Assignment with Replacement of Logical Conditions

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Chmielewski, Sławomir, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, and Chmielewski, Sławomir
Published: 2020
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16. Structural Decomposition in FSM Synthesis

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Chmielewski, Sławomir, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, and Chmielewski, Sławomir
Published: 2020
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17. FSM-Based Models of Control Units

Author: Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, Chmielewski, Sławomir, Angrisani, Leopoldo, Series Editor, Arteaga, Marco, Series Editor, Panigrahi, Bijaya Ketan, Series Editor, Chakraborty, Samarjit, Series Editor, Chen, Jiming, Series Editor, Chen, Shanben, Series Editor, Chen, Tan Kay, Series Editor, Dillmann, Rüdiger, Series Editor, Duan, Haibin, Series Editor, Ferrari, Gianluigi, Series Editor, Ferre, Manuel, Series Editor, Hirche, Sandra, Series Editor, Jabbari, Faryar, Series Editor, Jia, Limin, Series Editor, Kacprzyk, Janusz, Series Editor, Khamis, Alaa, Series Editor, Kroeger, Torsten, Series Editor, Liang, Qilian, Series Editor, Martin, Ferran, Series Editor, Ming, Tan Cher, Series Editor, Minker, Wolfgang, Series Editor, Misra, Pradeep, Series Editor, Möller, Sebastian, Series Editor, Mukhopadhyay, Subhas, Series Editor, Ning, Cun-Zheng, Series Editor, Nishida, Toyoaki, Series Editor, Pascucci, Federica, Series Editor, Qin, Yong, Series Editor, Seng, Gan Woon, Series Editor, Speidel, Joachim, Series Editor, Veiga, Germano, Series Editor, Wu, Haitao, Series Editor, Zhang, Junjie James, Series Editor, Barkalov, Alexander, Titarenko, Larysa, Mielcarek, Kamil, and Chmielewski, Sławomir
Published: 2020
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18. Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores.

Author: Titarenko, Larysa, Kharchenko, Vyacheslav, Puidenko, Vadym, Perepelitsyn, Artem, and Barkalov, Alexander
Subjects: COMPUTER systems, INFORMATION society, ALGORITHMS, POSSIBILITY, HARDWARE, CACHE memory
Abstract: Replacement policies have an important role in the functioning of the cache memory of processor cores. The implementation of a successful policy allows us to increase the performance of the processor core and the computer system as a whole. Replacement policies are most often evaluated by the percentage of cache hits during the cycles of the processor bus when accessing the cache memory. The policies that focus on replacing the Least Recently Used (LRU) or Least Frequently Used (LFU) elements, whether instructions or data, are relevant for use. It should be noted that in the paging cache buffer, the above replacement policies can also be used to replace address information. The pseudo LRU (PLRU) policy introduces replacing based on approximate information about the age of the elements in the cache memory. The hardware implementation of any replacement policy algorithm is the circuit. This hardware part of the processor core has certain characteristics: the latency of the search process for a candidate element for replacement, the gate complexity, and the reliability. The characteristics of the PLRUt and PLRUm replacement policies are synthesized and investigated. Both are the varieties of the PLRU replacement policy, which is close to the LRU policy in terms of the percentage of cache hits. In the current study, the hardware implementation of these policies is evaluated, and the possibility of adaptation to each of the policies in the processor core according to a selected priority characteristic is analyzed. The dependency of the rise in the delay and gate complexity in the case of an increase in the associativity of the cache memory is shown. The advantage of the hardware implementation of the PLRUt algorithm in comparison with the PLRUm algorithm for higher values of associativity is shown. [ABSTRACT FROM AUTHOR]
Published: 2024
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19. Programmable Logic Controllers

Author: Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Kacprzyk, Janusz, Series Editor, Barkalov, Alexander, Titarenko, Larysa, and Mazurkiewicz, Małgorzata
Published: 2019
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20. Implementation of Computational Algorithms in Embedded Systems

Author: Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Kacprzyk, Janusz, Series Editor, Barkalov, Alexander, Titarenko, Larysa, and Mazurkiewicz, Małgorzata
Published: 2019
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21. Introduction into Embedded Systems

Author: Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Kacprzyk, Janusz, Series Editor, Barkalov, Alexander, Titarenko, Larysa, and Mazurkiewicz, Małgorzata
Published: 2019
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22. Field Programmable Gate Arrays

Author: Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Kacprzyk, Janusz, Series Editor, Barkalov, Alexander, Titarenko, Larysa, and Mazurkiewicz, Małgorzata
Published: 2019
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23. Implementing Control Algorithms with FPGAs

Author: Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Kacprzyk, Janusz, Series Editor, Barkalov, Alexander, Titarenko, Larysa, and Mazurkiewicz, Małgorzata
Published: 2019
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24. Design of Embedded Systems

Author: Barkalov, Alexander, Titarenko, Larysa, Mazurkiewicz, Małgorzata, Kacprzyk, Janusz, Series Editor, Barkalov, Alexander, Titarenko, Larysa, and Mazurkiewicz, Małgorzata
Published: 2019
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25. Logic Synthesis for VLSI-Based Combined Finite State Machines

Author: Barkalov, Alexander, primary, Titarenko, Larysa, additional, Mielcarek, Kamil, additional, Mazurkiewicz, Małgorzata, additional, and Kawecka, Elżbieta, additional
Published: 2022
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26. Hardware Reduction for FSMs With Extended State Codes

Author: Barkalov, Alexander, primary, Titarenko, Larysa, additional, Mielcarek, Kamil, additional, and Mazurkiewicz, Małgorzata, additional
Published: 2024
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27. IPNES - Interpreted Petri Net for Embedded Systems

Author: Krzywicki, Kazimierz, Andrzejewski, Grzegorz, Zajac, Wojciech, Krolikowski, Tomasz, Barkalov, Alexander, and Titarenko, Larysa
Published: 2021
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28. Hardware Reduction for Mealy UFSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, and Bieganowski, Jacek
Published: 2018
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29. Hardware Reduction for Moore EFSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, and Bieganowski, Jacek
Published: 2018
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30. Hardware Reduction for Moore NFSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, and Bieganowski, Jacek
Published: 2018
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31. Hardware Reduction for Moore XFSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, and Bieganowski, Jacek
Published: 2018
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32. Finite State Machines and Field-Programmable Gate Arrays

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, and Bieganowski, Jacek
Published: 2018
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33. Linear Chains in FSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, and Bieganowski, Jacek
Published: 2018
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34. Introduction

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, and Bieganowski, Jacek
Published: 2018
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35. Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review.

Author: Barkalov, Alexander, Titarenko, Larysa, Bieganowski, Jacek, and Krzywicki, Kazimierz
Subjects: FINITE state machines, CIRCUIT elements, PROBLEM solving, SWITCHING circuits
Abstract: Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements. [ABSTRACT FROM AUTHOR]
Published: 2024
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36. Improving characteristics of LUT-based Mealy FSMs

Author: Barkalov Alexander, Titarenko Larysa, and Mielcarek Kamil
Subjects: fpga, lut, mealy fsm, structural decomposition, two-fold state assignment, energy consumption, Mathematics, QA1-939, Electronic computers. Computer science, QA75.5-76.95
Abstract: Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.
Published: 2020
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37. Separation of Input Variables for Optimization of the Mealy FSM Circuit

Author: Barkalov, Alexandr, primary, Titarenko, Larysa, additional, Golovin, Oleksandr, additional, Matvienko, Oleksandr, additional, and Saburova, Svitlana, additional
Published: 2023
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38. Design of EMB-Based Mealy FSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, Bazydlo, Grzegorz, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, and Bazydlo, Grzegorz
Published: 2016
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39. Hardware Reduction in Multidirectional Moore FSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, Bazydlo, Grzegorz, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, and Bazydlo, Grzegorz
Published: 2016
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40. Background of Finite State Machines and Programmable Logic

Author: Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, Bazydlo, Grzegorz, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, and Bazydlo, Grzegorz
Published: 2016
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41. Distribution of Class Codes in Moore FSMs

Author: Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, Bazydlo, Grzegorz, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, and Bazydlo, Grzegorz
Published: 2016
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42. Object Codes Transformation for Moore FSMs Object codes transformation (OCT)

Author: Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, Bazydlo, Grzegorz, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, and Bazydlo, Grzegorz
Published: 2016
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43. Field Programmable Gate Arrays in FSM Design

Author: Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, Bazydlo, Grzegorz, Kacprzyk, Janusz, Series editor, Barkalov, Alexander, Titarenko, Larysa, Kolopienczyk, Malgorzata, Mielcarek, Kamil, and Bazydlo, Grzegorz
Published: 2016
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44. Solving Load Balancing Problems in Routing and Limiting Traffic at the Network Edge

Author: Barkalov, Alexander, primary, Lemeshko, Oleksandr, additional, Yeremenko, Oleksandra, additional, Titarenko, Larysa, additional, and Yevdokymenko, Maryna, additional
Published: 2023
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45. Logic Synthesis for FPGA-Based Control Units

Author: Barkalov, Alexander, primary, Titarenko, Larysa, additional, Mielcarek, Kamil, additional, and Chmielewski, Sławomir, additional
Published: 2020
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46. Hardware Reduction for Lut–Based Mealy FSMs

Author: Barkalov Alexander, Titarenko Larysa, and Mielcarek Kamil
Subjects: mealy fsm, synthesis, fpga, lut, partition, encoding collections of output variables, Mathematics, QA1-939, Electronic computers. Computer science, QA75.5-76.95
Abstract: A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.
Published: 2018
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47. Finite State Machines with Operational Implementation of Transitions

Author: Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, Titarenko, Larysa, Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, and Titarenko, Larysa
Published: 2014
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48. Optimization of FSMs with Embedded Memory Blocks

Author: Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, Titarenko, Larysa, Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, and Titarenko, Larysa
Published: 2014
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49. Design Technique Based on Hierarchical and Parallel Specifications

Author: Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, Titarenko, Larysa, Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, and Titarenko, Larysa
Published: 2014
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50. Design of FSMs with Embedded Memory Blocks

Author: Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, Titarenko, Larysa, Sklyarov, Valery, Skliarova, Iouliia, Barkalov, Alexander, and Titarenko, Larysa
Published: 2014
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